Command line arguments inside a sequence

How to get command line values inside a sequence

+option=7 +carry='h37

I want to pass like this
'uvm_do_on (req.option == command line option; req.carry == command line carry;)
Can you help me for this type

This can be done by using plusargs in SystemVerilog. SV provides “$value$plusargs” to get a particular value from command line.

One drawback of using plusargs is that if you have multiple sequence objects, then all the objects will get same value of plusarg. If you want to set/get different values from command line for different sequence instances, then you should use config_db set from command line for the sequencer.

//Command line using plusargs:
+user_string=
//Sequence using plusargs:
$value$plusargs (user_string, variable)

//Command line using config_db:
+uvm_set_config_ int=<component path, sequencer path>,,
//Sequence using config_db:
uvm_config_db#(int)::get(null,m_sequencer.get_full_name(), “field_name”,variable);

Refer to this site and this doc for more information.

In reply to sharvil111:

The uvm_cmdline_processor is better than using $value$plusargs.

In reply to dave_59:

Hi @dave_59 ,

Is there a reason as to why uvm_cmdline_processor is better than $value$plusargs ?

In reply to szy0014:
https://verificationacademy.com/forums/uvm/uvmcmdlineprocessor#reply-87187