I have three register models generated using ralgen (the third model was not supplied with ralf). Can I combine these register models into one file and instantiate it in TB instead of declaring all three files.
My initial thought is
class uni_rg_model extends uvm_block;
//same for 2,3
virtual function build();
adding default_map of model 1;
repeating for all reg models
Can we do this and will we have any issues while accessing registers? Again in env connecting to adapter as I have one apb adapter and all three register models run on apb interface