in the code below, the compiler complains about a syntax error at the line with uvm_config_db, any hints??
`timescale 1ns/1ps
module test ;
class config_testt extends uvm_object ;
`uvm_object_utils(config_testt);
rand int posedge_var = 0 ;
function new (string name = "config_test") ;
super.new(name);
endfunction
endclass
bit clk = 1'b0 ;
config_testt config_test0 ;
intf0 intf0_inst (clk) ;
adder adder0 (intf0_inst.ins_outs) ;
initial begin forever #10 clk = ~clk ; end
//register the interface handle in the config db.
initial begin
config_test0 = new("config_test0");
//config_test0 = config_test::type_id::create("config_test0", "");
if(!config_test0.randomize) begin
`uvm_fatal("(test): config_test0 failed to randomize", "") ;
end
uvm_config_db#(virtual config_testt)::set(null,"adder_model_test.env","config",config_test0);
`uvm_info("value of cfg: ", $sformatf("%0d", config_test0.posedge_var), UVM_LOW);
run_test ("adder_model_test") ;
end
endmodule