Co-Verification Environment Issue

UVM
,
1

Hi.

I’m trying to setup the co-verification between reference c++ code and UVM and compare Reference C++'s output and UVM output.

But some current situation is very tricky for me.

  1. Reference C++ make output vector.
  2. The output vector from (1) used for UVM simulation.
  3. Reference C++ operated by randomized constraint variable from UVM.

Problem : UVM simulation Need to regression with randomize but Reference C++ code should be run first by using UVM simulation randomized input variable.

So In this situation, What should I do for Co-Verification between UVM and C++ code?

2

In reply to UVM_LOVE:

You have to embed your C++ subroutine into a SV component and connect his component to your UVM environment.

3

In reply to chr_sue:

In reply to UVM_LOVE:
You have to embed your C++ subroutine into a SV component and connect his component to your UVM environment.

Currently, I can’t afford to embed Reference C++ code as subroutine into a SV component. Because That C++ model is came from another company and they don’t know systemverilog as well.
Do I have to breakdown pure c++ code into SV subroutine? such as by using DPI-C techniques?

4

In reply to UVM_LOVE:

The answer to your question can be complicated without knowing how the model is structured to be used in a pure C++ environment. Can it be wrapped in a C function? How does it expect input and output to be handled?

5

In reply to dave_59:

In reply to UVM_LOVE:
The answer to your question can be complicated without knowing how the model is structured to be used in a pure C++ environment. Can it be wrapped in a C function? How does it expect input and output to be handled?

Fortunately, I could resolve it with $system() function.
For example,
sys_cmd = {“/user/bin/python3 /user/data/calc.py”, lut_r_sd, pure_tap[0]};
$system(sys_cmd);

like this way.