Clocking problem

Hello,

I am trying to verify MIPS-32 controller module for a particular instruction.
In my testbench, I have given 32-bit instr = 8’h03177920. For this particular instruction, I should get my Controller_out = 1100000010.

Now, when I run my testbench, I am getting delayed output. I think I am not giving the clock right.

I will be grateful if anyone could see to my problem.

Thankyou

In reply to SV26:

Your playground link is not public. Please share it …
BTW, looks like your design has a problem. I do not believe it is caused by the clocking scheme.

In reply to chr_sue:

Hello,

Thank you for replying, I have made the link public.

I have tested the design using ModelSim, it was working fine. I hope you can trace the error.

In reply to SV26:

Could you please explain what you mean with ‘delayed output’? The log-file is showing how the code is implemented.

In reply to SV26:

In the log file.
As you can see in the first 2 lines, @5, instead of driver, it is showing the monitor.

[b]UVM_INFO @ 0: reporter [RNTST] Running test my_test…
UVM_INFO monitor.sv(27) @ 5: uvm_test_top.ENV.AGNT.MON [MONITOR: ] Monitoring the transaction:
instr = 00000000
Controller Output = 0000000000

I want the testbench to drive he input first, take the output to the interface and provide it to the monitor.

After the above log file, now it drives the input as inst= 03177920, but the output still remains Controller_out=0000000000. It should be 11000000110.

UVM_INFO Driver.sv(30) @ 5: uvm_test_top.ENV.AGNT.DRIV [DRIVER: ] Driving the instruction to the Controller: 03177920
UVM_INFO monitor.sv(27) @ 15: uvm_test_top.ENV.AGNT.MON [MONITOR: ] Monitoring the transaction:
instr = 03177920
Controller Output = 0000000000

Later, it gives the correct output in the following log…

UVM_INFO Driver.sv(30) @ 15: uvm_test_top.ENV.AGNT.DRIV [DRIVER: ] Driving the instruction to the Controller: 03177920
UVM_INFO monitor.sv(27) @ 25: uvm_test_top.ENV.AGNT.MON [MONITOR: ] Monitoring the transaction:
instr = 03177920
Controller Output = 1100000010

In reply to SV26:

OK, I understand.
With respect what comes first, driver or monitor you do not have any influence because all run_phases are executed in a fork/join. If you want the monitor becoming active after the driver you have to control this with an additional event or another mechanism.
THe driver display you the intruction as it is provided to the DUT. The valid output from the DUT comes 1 clock cycle later.
It is correct what you see.

In reply to chr_sue:

I tried to apply the concept of events and was able to sync my driver and monitor, but, was unable to display my monitor and scoreboard values for the last transaction. Can you tell me why?

In reply to SV26:

I did not check all the details. I was only inserting an additional `uvm_info in the driver and the monitor. This results in showing only 2 seq_items, i.e. there is something additionally wrong.
When using events inside the same agent you do not need the global event_pool. You can simply use the uvm_event.

In reply to chr_sue:

I just added a delay of #10 inside my sequence, and now it is working fine. I do not know the reason though.