I am trying to verify MIPS-32 controller module for a particular instruction.
In my testbench, I have given 32-bit instr = 8’h03177920. For this particular instruction, I should get my Controller_out = 1100000010.
Now, when I run my testbench, I am getting delayed output. I think I am not giving the clock right.
I will be grateful if anyone could see to my problem.
OK, I understand.
With respect what comes first, driver or monitor you do not have any influence because all run_phases are executed in a fork/join. If you want the monitor becoming active after the driver you have to control this with an additional event or another mechanism.
THe driver display you the intruction as it is provided to the DUT. The valid output from the DUT comes 1 clock cycle later.
It is correct what you see.
I tried to apply the concept of events and was able to sync my driver and monitor, but, was unable to display my monitor and scoreboard values for the last transaction. Can you tell me why?
I did not check all the details. I was only inserting an additional `uvm_info in the driver and the monitor. This results in showing only 2 seq_items, i.e. there is something additionally wrong.
When using events inside the same agent you do not need the global event_pool. You can simply use the uvm_event.