Hey all,
I have a pipelined driver for a bus protocol, when i apply a signal, the bus behaviour for that signal is delayed with one cycle. I’ve been debugging the code and i might think that the get next item is taking place in 0 simulation time. When i apply that signal, it stills get the next item then drive its signals.
Is there any solution to this problem?
In reply to abdelaali_21:
It is difficult to provide advice without seeing your code. Can you provide an example on EDA Playground which reproduces your issue?
In reply to cgales:
Sorry, i can’t share it, it’s confidential. However, to elaborate more, its like ahb bus protocol. when i get next item, i assign values of addr phase to coressponding signals then i do the data phase. But i ran a reset process, that senses the enabling of it. at that time i assign decribe bus signal bahaviour toward resetn.
But the thing that exhausted me is bahaviour is delayed with one cycle. in other words, the addr phase of the next transfer takes place even if reset is enabled. I checked hard and found that get item item gives item one colck cycle before.
In reply to abdelaali_21:
It’s still not clear to me what you are describing. Are you using clocking blocks? These could result in delay issues, especially if you are generating the reset from an external source. There could be other issues as well, but I would only be guessing without seeing any code.