Clock generation inside Driver

UVM
1

Hi,
Normally, I used to generate clock in top module. But,now I have a separate driver for clocks generation. I use forever to generate clock. But,simulation is not exiting.Please suggest me how to create clock from driver and drives to interface.

I saw a similar example in verification academy:

task my_driver::clk_gen();
bit clk;
this.clk_en = 1;
forever begin
if (this.clk_en == 1)begin
#(`CLK_PERIOD); //This works !!!
clk = ~clk;
this.vif.tb_clk = clk;

end

end
endtask: clk_gen

I tried this. But still I am facing the same issue.Please suggest.

Thanks in advance,
Roopa

2

In reply to roopatoms:

If there is no special need you should generate your clocks in the toplevel module. This makes your life easy.
If you need the clock generation in a driver/agent you can use ‘stop_stimulus_generation’. See the UVM Reference Manual for more details.

3

In reply to chr_sue:

can you please give some more explanation for stop_stimulus_generation.

4

In reply to roopatoms:

Hi Roopa,

It is a system verilog code or UVM code.

  • if system verilog code. You can wrap it around dynamic process and Kill it when not necessary.
    -If UVM if there are no pending objections. simulation will stop even-though forever loop is used.

Thanks
Saravanan