Clk enable

UVM
, ,
1

Hi

I added enable to clock in testbench

 initial begin//{
      forever
        begin//{
        if(spir180_interfaces_i.spi_sigs.spi_ce==1)begin//{
          @(negedge spir180_interfaces_i.spi_sigs.spi_ce)begin//{
              repeat (`SPI_START_CLK_ACTIVE)@ (posedge tb_clk);
              clk_en =1;
          end//}
        end//}
        else if(spir180_interfaces_i.spi_sigs.spi_ce==0)begin//{
           @(posedge spir180_interfaces_i.spi_sigs.spi_ce)begin//{
              repeat (`SPI_START_CLK_DECTIVE + 6 )@ (posedge tb_clk);
              clk_en =0;
          end//}
        end//}
        else 
        @ (posedge tb_clk);
      end//}
   end//}

my test failed on :
UVM_FATAL 10500000.0ns /tools/accellera/uvm-1.1d/src/base/uvm_phase.svh (1268) reporter|PH_TIMEOUT: Explicit timeout of 10500000.0ns hit, indicating a probable testbench issue

what is the problem?
Thanks, in advance

2

In reply to saraTel:

Good question, but no answer possible without seeing more code.