Hello Sir,
I am new to the integration of SystemC and UVM components. I have a scenario in my environment where i have to convert SystemVerilog class into verilog module. Can you suggest some of the steps.
Regards
Sunil S.
In reply to sunils:
Your first step might be to hire a consultant. I am available :)
But seriously, you need to explain a lot further because you first mention “integration” of SystemC and UVM components. And then you mention “converting” a SystemVerilog class (not a SystemC class) into a Verilog module.
So by “integration” do you mean using models from both languages at the same time, or do you mean translating a model from one language to another? And in either case you will need to provide information at a high level of what these models do, because there are many different ways to accomplish this.