I am trying to change the initial value of an internal DUT counter using a force statement in SV interface that binds to the DUT module containing the signal. My DUT is in VHDL and my testbench is an SV/UVM testbench. I am able to force the signal to desired value at reset, however I cannot release the signal after reset is deasserted. Here’s a simplified example of my code:
================== DUT Code ==================
entity dut is
port (clk in std_logic;
rst_n in std_logic);
end dut;
architecture dut_arch of dut is
signal count : std_logic_vector(31 downto 0);
process (clk, rst_n)
begin
if (rst_n == 0) then
count <= (others => '0');
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process
end dut_arch
============== Testbench Code =================
interface dut_if (input rst_n, clk);
bit enable;
bit[31:0] init_count;
function force_count(bit[31:0] count_value);
init_count = count_value;
enable = 1;
endfunction : force_count
always @(posedge clk)
begin
if (enable && !rst_n)
begin
force dut.count = init_count;
end
else if (enable)
begin
release dut.count;
end
end
endinterface : dut_if
module tb_top();
bit clk, rst_n;
bind dut dut_if dut_if_inst;
virtual dut_if dut_vif;
dut_vif = dut_inst.dut_if_inst;
//Clk Gen
always #10ns clk = ~clk;
//Gen Reset
initial
begin
rst_n = 0;
#100ns;
rst_n = 1;
end
// enable count value change
initial
begin
dut_inst.dut_if_inst.force_count(32'hFFFFFFF00);
end
dut dut_inst(.*);
endmodule
The only real difference between my actual code and the above code is that I pass interface handle (dut_vif) to UVM tb using config_db. The TB env call the force_count function during end_of_elaboration UVM phase. In the waves, I can see the count value getting forced to 32’hFFFFFF00 during reset. However, the count signal doesn’t get released when reset is deasserted.