Lets assume i have an interface with have inside it data1[7:0] and data2[15:0]
and i want to write 2 modports. in 1 the output will be data1 (and will be called data) and the other modport will have for output the data2 (and will call it data).
You use modport expressions for this. This is similar to Verilog’s port expression where you can name a port different from the signal it is connected to.
interface itf;
bit [7:0] data1;
bit [15:0] data2;
modport mod1(output .data(data1));
modport mod2(output .data(data2));
endinterface
module m(itf ip);
initial $display("%m %h",ip.data);
endmodule
module top;
itf if1();
m m1(if1.mod1);
m m2(if1.mod2);
// need separate virtual interface variables because data cannot be dynamically typed
virtual itf.mod1 v1 = if1;
virtual itf.mod2 v2 = if1;
initial $displayh(v1.data);
initial $displayh(v2.data);
endmodule