hai,
In verilog change of a each siganl variable we are able to capture by
always@(posedge enable or negedge of rst or data )
begin
end
to get this functionality in uvm drive what we have to use in uvm driver ?
hai,
In verilog change of a each siganl variable we are able to capture by
always@(posedge enable or negedge of rst or data )
begin
end
to get this functionality in uvm drive what we have to use in uvm driver ?
In reply to nana:
uvm_driver drives the data /control information based on uvm_sequence_item.
Data / control information is observed by the uvm_monitor and send to checker using TLM port connection.
If you want to drive the data through uvm_driver based on the changes on the particular variable, then you need to implement the reactive driver