I am using Questasim 10.7c. I am trying to compile my code but i am getting following errors.
– Compiling package ram_pkg
– Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
** Note: (vlog-2286) E:/Questasim/examples/180121/ram_pkg.sv(6): Using implicit +incdir+C:/questasim64_10.7c/uvm-1.1d/…/verilog_src/uvm-1.1d/src from import uvm_pkg
** Error: (vlog-13069) ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(10)
** at E:\Questasim\examples\180121\uvm_wr_txn_macro.sv(34): near “constraint”: syntax error, unexpected “SystemVerilog keyword ‘constraint’”.
** Error: ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): (vlog-2730) Undefined variable: ‘short_txn’.
** Warning: ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): (vlog-2953) Incorrect usage of keyword ‘static’.
** Error: (vlog-13069) ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): near “function”: syntax error, unexpected function, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.
** Error: ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): ‘create’ already exists; must not be redefined as a function.
** Error: (vlog-13069) ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.
** Error: ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): (vlog-2730) Undefined variable: ‘tmp’.
** Error (suppressible): ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): (vlog-2388) ‘type_name’ already declared in this scope (write_txn).
** Error: ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): ‘get_type_name’ already exists; must not be redefined as a function.
** Error: ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): ‘__m_uvm_field_automation’ already exists; must not be redefined as a function.
** Error: (vlog-13069) ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.
** Error: ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): Illegal declaration after the statement near line ‘5’. Declarations must precede statements. Look for stray semicolons.
** Error: (vlog-13069) ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** while parsing macro expansion: ‘uvm_object_utils’ starting at E:\Questasim\examples\180121\short_txn.sv(5)
** at E:\Questasim\examples\180121\short_txn.sv(5): near “end”: syntax error, unexpected end.
** Error: ** while parsing file included at E:/Questasim/examples/180121/ram_pkg.sv(12)
** at E:\Questasim\examples\180121\short_txn.sv(10): ‘super.new()’ call can be made only from within a class constructor.
Below are the codes i have written
File 1 - ram_pkg.sv
package ram_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "tb_defs.sv"
//`include "uvm_write_txn.sv"
`include "uvm_wr_txn_macro.sv"
`include "short_txn.sv"
/*
`include "uvm_ram_wr_drv.sv"
`include "uvm_ram_wr_agent.sv"
`include "uvm_ram_env.sv"
`include "uvm_ram_wr_test.sv"
*/
endpackage
File 2 - factry_over_uvm.sv
import uvm_pkg ::*;
import ram_pkg ::*;
module fact_top1;
write_txn write_txnh;
function void build ();
write_txnh = write_txn :: type_id :: create ("write_txnh");
assert (write_txnh.randomize());
write_txnh.print(uvm_default_table_printer);
write_txnh.print();
endfunction
initial
begin
repeat(5)
build();
factory.set_type_override_by_type (write_txn :: get_type(), short_txn :: get_type());
repeat (5)
begin
build();
end
end
endmodule
File 3 - tb_defs.sv
`define RAM_WIDTH 64
`define ADDRESS_SIZE 12
typedef enum bit {BAD_TXN, GOOD_TXN} addr_t;
File 4 - uvm_wr_txn_macro.sv
class write_txn extends uvm_sequence_item;
//`uvm_object_utils (write_txn)
rand bit [`RAM_WIDTH-1 : 0] data;
rand bit [`ADDRESS_SIZE-1 : 0] addr;
rand bit write;
rand addr_t txn_type;
rand bit [63:0] txn_delay;
`uvm_object_utils_begin (write_txn)
`uvm_field_int (data, UVM_ALL_ON);
`uvm_field_int (addr, UVM_ALL_ON);
`uvm_field_int (write, UVM_ALL_ON);
`uvm_field_enum (addr_t, txn_type, UVM_ALL_ON);
`uvm_field_int (txn_delay, UVM_ALL_ON);
`uvm_object_utils_end
constraint a { data inside {[20:90]};
addr inside {[0:200]};
txn_type dist {BAD_TXN := 2, GOOD_TXN := 30};}
function new (string name = "write_txn");
super.new (name);
endfunction
function void post_randomize;
constraint b {txn_type == BAD_TXN -> addr = 6000;}
//constraint b {addr = 6000;}
`uvm_info ("Post_randomize", "Executed Post Randomize", UVM_LOW)
endfunction
endclass
File 5 - short_txn.sv
class short_txn extends write_txn;
`uvm_object_utils(short_txn)
constraint c {addr == 10;}
function new (string name = "short_txn");
super.new (name);
endfunction
endclass