Cannot predict while reg is being accessed

I am generating a reg bus transaction from a sequence using

reg_block.iritating_reg.write()

and in the environment ref model:

reg_block.iritating_reg.predict()

(no I am not using a predictor)
I get the WARNING: cannot predict while reg is being accessed, and the regs mirrored value is not updated
From what I understand this is because the monitor finishes to collect the transaction
and activates the analysis port before the driver.(cannot be changed)
Is there a way to bypass this warning so the reg will be updated?