In reply to cgales:
UVM divides up the testbench into separate blocks, each with its own job. A sequence creates transaction objects and sends them out. A sequencer receives transaction handles from one or more sequences and arbitrates between them, and sends those handles to the driver. The driver receives the handles and sends the values to the design, either by directly driving signals, or communicating through a bus functional model (BFM) with methods in an interface.
