Can uvm register model which support backdoor operation included in a package?

UVM
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1

Hi all:
The uvm register model backdoor use direct hierarchy reference register of DUT. Now register model is constructed in env:

class ahb_env extends uvm_env;
    ahb_reg_model reg_model;
    ...
    function void build_phase(uvm_phase phase);
        reg_model = ahb_reg_model::type_id::create("reg_model", this);
         ...
    endfunction : build_phase
endclass : ahb_env

Then both ahb_reg_model & ahb_env is included in env_pkg:

package env_pkg;
    `include "ahb_reg_model.sv"
    `include "ahb_env.sv"
    ...
endpackage

In test_top:

module test_top;
    import env_pkg::*;
    ahb_reg_system DUT (...);
    ...
endmodule

But register model can’t hierarchy reference signal out of the scope of package, how to deal with it?
Thanks!

2

The backdoor paths in the register model are accessed via DPI, not through direct hierarchical access - that is how the package scoping restrictions are avoided.

3

In reply to jcraft:

Thank you very much!