Can UVM component exist in a OVM testbench during simulation : In my OVM testbench, I would like to include a component which is derived from UVM classes. I am concerned on the phasing of both methodologies.
In reply to minu_yadav@mentor.com:
They can exist independently of each other as they are separate packages. You can synchronize the time consuming phases with each other by having the phase that finishes first in one package wait for the corresponding phase in the other package to end.