Can a module be instantiated in a class, in UVM ?
Can a verilog module be instantiated inside a (driver) class? If yes, then can I connect the incoming packets to any input signal of that module instance, in the run phase() of driver? And if not, then how to connect the signals of that module to the driver. I dont want to connect the driver to the systemverilog interface, but to the signals of this verilog module.
Can some one throw some light on this.
No, you can't instantiate a module inside a class. Module are static objects that are instantiated before time 0 during elaboration. Classes are dynamic objects that are constructed at or after time 0 during simulation.
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