Hello All,
Can a verilog module be instantiated inside a (driver) class? If yes, then can I connect the incoming packets to any input signal of that module instance, in the run phase() of driver? And if not, then how to connect the signals of that module to the driver. I dont want to connect the driver to the systemverilog interface, but to the signals of this verilog module.
Can some one throw some light on this.
Thanks,
Swapnil
No, you can’t instantiate a module inside a class. Module are static objects that are instantiated before time 0 during elaboration. Classes are dynamic objects that are constructed at or after time 0 during simulation.
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In reply to dave_59:
Dear Sir,
If a module cant be instantiated inside a class, then plz help me with this issue. I need to convert the packet bytes from parallel to serial because my DUT takes only serial bits. I am trying to use parallel to serial in a module and trying to connect it to the Driver inside the run phase. How would this work? I am not getting any idea. Plz guide me for this.
Thanks,
Swapnil
In reply to r_vaidhyanathan:
Hello r_vaidhyanathan,
Thanks for your suggestion. So if I am putting the logic of parallel to serial inside a task, I can call this task during the run phase() of driver ? Will it work properly without giving simulation errors, because I believe parallel to serial would work on the clock during simulation time. Correct me if I am wrong and give me guidance.
Thanks,
Swapnil
In reply to swapnilm:
Yes, You can call this task in your driver’s run_phase. Ofcourse, parallel to serial logic works on the clock, and since the driver will have the handle of your virtual interface, you can use the interface’s clock for your logic.