Can I use while statement substitute by wait statement or vice versa in uvm?

UVM
, ,
1

Hi

Can I use while statement substitute by wait statement or vice versa in uvm?

// Code your testbench here
// or browse Examples
module top;
  bit temp =1;
  initial begin
    $display("ACODE");
     
    while(temp!=0) begin
	    #5;
	    $display("waiting in whle loop");
  	end
    
    wait(temp==0)  $display($time,"BCODE");
 
    
  end
  
  initial begin
    
    #30;
    temp=0;
  end
endmodule

I think there is no difference between them, If I wrong, Would you please help me for understanding what they difference ?

2

In reply to UVM_LOVE:

The difference is the while loop samples temp in a periodic #5 delay loop. If temp changes in the middle of that period, it only can exit the loop st the end of the period when it evaluates the expression. If the delay is very small, you could wind up evaluating the expression many times before existing the loop. The wait statement gets triggered by the change an exits immediately when temp==0.

3

Agree with dave_59.

I have used “@(posedge system_clk)” under while loop to substitute for wait statement. This exactly imitates the wait statement when the condition in your wait statement is sampled by system_clk too.