Can I use uvm_config_db initial begin?

UVM
, ,
1

I’m trying to coneect interface with uvm_config_db set/get in intial block.
But Compiler said that Component does not refer to a scope.
I didn’t get it because I set uvm_config_db at initial begin, why does it say it does not refer to a scope?

  initial begin
      uvm_config_db #(virtual i2c_intf)::set(null,"*", "i_i2c_intf", i_i2c_intf);
    
    if (!uvm_config_db #(virtual i2c_intf)::get(null, "", "i_i2c_intf", i_i2c_intf))            
        `uvm_fatal("FATAL MSG", "Virtual Interface Not Set Properly");

  end

But problem is that I got error about Component name ‘i_i2c_intf’ does not refer to a scope.

QuestaSim-64 vlog 2021.3_1 Compiler 2021.08 Aug 15 2021
Start time: 21:42:23 on Feb 18,2022
vlog -writetoplevels questa.tops -timescale 1ns/1ns "+incdir+/playground_lib/uvm-1.1d/src" -L /usr/share/questa/questasim//uvm-1.1d design.sv testbench.sv 
-- Compiling module adder
-- Compiling interface i2c_intf
-- Compiling interface axi_intf
-- Compiling interface ahb_intf
** Note: (vlog-2286) testbench.sv(11): Using implicit +incdir+/usr/share/questa/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg
-- Compiling package testbench_sv_unit
-- Compiling module test
-- Compiling module tbench_top
-- Importing package /usr/share/questa/questasim//uvm-1.1d.uvm_pkg (uvm-1.1d Built-in)
** Error: testbench.sv(29): Component name 'i_i2c_intf' does not refer to a scope.
** Error: testbench.sv(30): Component name 'i_i2c_intf' does not refer to a scope.
** Error: testbench.sv(31): Component name 'i_i2c_intf' does not refer to a scope.
End time: 21:42:24 on Feb 18,2022, Elapsed time: 0:00:01
Errors: 3, Warnings: 0
Exit code expected: 0, received: 1

this is code from (2) - EDA Playground . for understanding my problem

`include "interface.sv"
`include "test.sv"

module tbench_top;
  	
    import uvm_pkg::*;      //Add for uvm_config_db
   `include "uvm_macros.svh"//Add for uvm_config_db
  
  //creatinng instance of interface
 // i2c_intf i_i2c_intf();
  axi_intf i_axi_intf();
  ahb_intf i_ahb_intf();
  
  
 
  test t1(i_i2c_intf, i_axi_intf, i_ahb_intf);  
  
 
  adder DUT (
    .a(i_i2c_intf.a),
    .b(i_i2c_intf.b),
    .c(i_i2c_intf.c),
    .a0(i_axi_intf.a0),
    .b0(i_axi_intf.b0),
    .c0(i_axi_intf.c0),
    .a1(i_ahb_intf.a1),
    .b1(i_ahb_intf.b1),
    .c1(i_ahb_intf.c1)

   );
  
  
  initial begin
      uvm_config_db #(virtual i2c_intf)::set(null,"*", "i_i2c_intf", i_i2c_intf);
    
    if (!uvm_config_db #(virtual i2c_intf)::get(null, "", "i_i2c_intf", i_i2c_intf))            
        `uvm_fatal("FATAL MSG", "Virtual Interface Not Set Properly");

  end
endmodule

Would you may guide me how do I get Component name ‘i_i2c_intf’ which is not refer to a scope.?

2

In reply to UVM_LOVE:

  1. why not use uvm_env if you are using uvm_config_db?

  2. you should call config_db::get method inside your env class, not in tb_top, ideally in build_phase. or somewhere after constructor new();

  3. test should be class extended from uvm_test rather than module if you really want to use UVM.

  4. looks like you are new to how systemverilog testbench works, and kind of confused between UVM and SV testbench.

3

In reply to Jeff_Li_90:

In reply to UVM_LOVE:

  1. why not use uvm_env if you are using uvm_config_db?
  2. you should call config_db::get method inside your env class, not in tb_top, ideally in build_phase. or somewhere after constructor new();
  3. test should be class extended from uvm_test rather than module if you really want to use UVM.
  4. looks like you are new to how systemverilog testbench works, and kind of confused between UVM and SV testbench.

you are right it based on systemverilog so. it was not good from start.
I will close this case.

Thanks you for reply.