Can I use the same driver to drive two different DUTS

Hi, I have two DUTs and both the DUTS have almost the same inputs, except 1 input. Can I use the same input UVC for both the DUTs and include all the signals ? or should I create two different input UVCs with almost the same signals?
example: DUT1 needs inputs signals A,B,C and DUT2 needs input signals A,B,D.
Should I create a driver that can drive all A,B, C, D ?
or crate one input UVC and interface that can drive A,B,C and the 2nd input UVC and interface that can drive A,B,D.

In reply to Praseetha:

Are the A,B,C & D are data signals or control signals?
If data then you can use the same UVC, but you also need to see how you source the data(using transaction) to the Driver and how does the transaction differentiates these A, B, C & D in your environment.

In reply to yourcheers:

All of them are data signals, in that case if I can drive it using the same driver I was thinking I could try the following:

  1. Create 4 sets of sequences in my master sequences_lib:
    • 1 sequence with A,B
    • 1 sequence with c
    • 1 sequence with D
  2. Then in my driver, I can drive them one after the other by creating an enumerated datatype to choose which sequence I want to run.

Will this method be okay?
But my only concern is the driver will be driving more signals than dut can take. is that okay?

In reply to Praseetha:

You should differentiate between signals and data members of your seq_item For data it might be OK.
Nobody is forcing you tp seperate your data members in different sequences/seq_items.

class my_item extends uvm_sequence_item;
    // registration with the factory
  rand int A;
  rand int B;
  rand int C;
  rand int D;
  // constructor
endclass

class my_seq extends uvm_sequence #(my_item);
   // registration with teh factory
   // constructor
   task body();
      repeat(50);
       `uvm_do(my_item)
   endtask
endclass

In your driver you can use the generated seq_items with the corresponding values of the data mambers A, B, C and D.