Can I use ">>" on the configure function in RAL model?

I’m trying to make a RAL model as below
TOPINT_t has reset value 0x0A which I was implement

class TOPINT_t extends uvm_reg;
                        
  rand uvm_reg_field LDO_INT;
  rand uvm_reg_field SW_INT;
  rand uvm_reg_field SW_BB_INT;
  rand uvm_reg_field CHG_INT;
  rand uvm_reg_field SYS_INT;
  rand uvm_reg_field reserved0;
                        
  virtual function void build();
    LDO_INT = uvm_reg_field::type_id::create("LDO_INT");                          
    LDO_INT.configure(this, 1, 0, "RO", 0, 8'hA>>0, 1, 1, 1);   
    SW_INT = uvm_reg_field::type_id::create("SW_INT");
    SW_INT.configure(this, 1, 1, "RO", 0, 8'hA>>1, 1, 1, 1);    
    SW_BB_INT = uvm_reg_field::type_id::create("SW_BB_INT");
    SW_BB_INT.configure(this, 1, 2, "RO", 0, 8'hA>>2, 1, 1, 1); 
    CHG_INT = uvm_reg_field::type_id::create("CHG_INT");                          
    CHG_INT.configure(this, 1, 3, "RO", 0, 8'hA>>3, 1, 1, 1);   
    SYS_INT = uvm_reg_field::type_id::create("SYS_INT");
    SYS_INT.configure(this, 1, 4, "RO", 0, 8'hA>>4, 1, 1, 1);   
    reserved0 = uvm_reg_field::type_id::create("reserved0");
    reserved0.configure(this, 3, 5, "RO", 0, 8'hA>>5, 1, 1, 1); 

  endfunction

But I’m confused LDO_INT is 1bit register then can I use “>>” to the configure() function ?
and 8’hA>>0 is correctly implemented or not.

In reply to UVM_LOVE:

It’s your code you are showing here. You should know what your objection is.
8’hA>>0 means you do not shift anything.

In reply to chr_sue:

In reply to UVM_LOVE:
It’s your code you are showing here. You should know what your objection is.
8’hA>>0 means you do not shift anything.

 addr_reg_type extends uvm_reg;                
            
  rand uvm_reg_field addr;
          
  virtual function void build();                    
    addr = uvm_reg_field::type_id::create("addr");  
    addr.configure(this, 4, 0, "RW", 0, `UVM_REG_DATA_WIDTH'h2>>0, 1, 1, 1);
    add_hdl_path_slice("addr_reg", 0, 4);
    addr.set_reset(`UVM_REG_DATA_WIDTH'h3>>0, "SOFT");   
    uvm_pkg::uvm_resource_db#(bit)::set({"REG::",get_full_name()}, "NORMAL", 1);
    wr_cg.set_inst_name($sformatf("%s.wcov", get_full_name()));
    rd_cg.set_inst_name($sformatf("%s.rcov", get_full_name()));
  endfunction

Sir,

I came across

 uvm_pkg::uvm_resource_db#(bit)::set({"REG::",get_full_name()}, "NORMAL", 1);

Could you please help me to understand what the usage this is?

For example, uvm_resource_db#(int)::set(“uvm_test_top.env”, “my_int”, 1024); is good for readability.
But uvm_pkg::uvm_resource_db#(bit)::set({“REG::”,get_full_name()}, “NORMAL”, 1); is don’t know what does this mean.

In reply to UVM_LOVE:

First remark. You should never use uvm_resource_db. Instead use uvm_config_db.
Wrt your question. uvm_resource_db has 3 arguments.
1st is the context. In your case this is the concatenation of REG:: and get_full_name().
What get_full_name() returns depends on the place where you are doing this set.
In a sequence it does not return any hierarchy. In a component it returns the complete hierarchical path of this component.