Can I get more basic UVM examples to improve my knowledge?

UVM
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1

I have been working as a Design Verification Engineer for a year now and am learning UVM hands-on.

But, I would have learned more had I practiced UVM by myself by just having a basic DUT and writing UVM objects+components to verify the DUT.
I found a couple of examples online:
1 - UVM TestBench Example code - verificationguide.com - EDA Playground
2 - SystemVerilog TestBench Example code - Adder Monit - EDA Playground

Apart from these two, can I get similar examples that I can use as references and build the TB by myself on my end?

I really appreciate any help that anyone can provide.

2

In reply to brain_storm:

The UVM Cookbook has a lot of examples that you can reference.