Calling a task() in top_module in uvm_sequence or uvm_test

Hi,
I am trying to call a task written in top module from UVM sequence, and it does not recognize the task, This used to work for me in uvm 1.1d and currently i am using uvm 1.2. Is there any thing changed? is there a right way to do this?

class soc_initialize_power_seq extends soc_vseq_base;
   `uvm_object_utils (soc_initialize_power_seq)
      //   uvm_root top;
      //   uvm_coreservice_t cs;

   function new (string name= "soc_initialize_power_seq");
      super.new (name);
      set_automatic_phase_objection (1);
   endfunction
   extern virtual task body ();
endclass : soc_initialize_power_seq

task soc_initialize_power_seq::body ();
   super.body();
   	TOP.initialize_power(); // how to call a Task in my Testbench Top in
        //   Error: illegal location for a hierarchical name though i copied from GUI
      //--- get root ----------- This also does not work
      //   cs = uvm_coreservice_t::get();
      //   top = cs.get_root();
      //-------------------------
      //   top.initialize_power();
      // Error is :
      //  initialize_power is not a class item.
      //-------------------------
endtask : body

//--I have a task in my Top module
  task initialize_power();
	
	//$display("initialize power --> supply is turned on");
	//	switch_supply = 1'b1;
  endtask: initialize_power

In reply to shrac123:

This is not a UVM issue. If your class is defined in a package, SystemVerilog does not allow references outside that package except another package. You can either wrap a call inside a interface that you call via a virtual interface, or use an abstract/concrete class pattern. See Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection | Verification Academy