I have a register layer modeling the DUT address space. In addition I have a custom protocol which supports single and burst trunsfers. The naming might be misleading, I’ll explain:
Single transfer - is transfer where the packet transmitted contains any number of the following: an address word and a data byte (3 bytes total, N times in a single transaction).
Burst transfer - is transfer where the packet transmitted contains an address word and a stream of data bytes. Each byte should be written to a consecutive register address.
I’m trying to understand how to implement those transactions using the UVM RAL facilities. From what I currently understand and have implemented I can generate a single access to single register at a time.
Any help would be appriciated.