I was using some tools to verify some of the designs in my previous job. I have changed my company and I do not have verification tool licenses up here. I am trying to build a test environment based on UVM on Vivado. Vivado is somehow supporting Systemverilog, so I thouht I must able to build testbenches based on UVM too. Yet, I am getting some problems while running the behavioral simulation. I do know that I won't be able to get coverage on this environment but I expected to see at least simulation. It seems like there will be bunch of issues. Is there a way to make this work on this environment? Have you ever tried?
If there is not, is there any suggestion that you can give me to build a test environment for the designs I have? Is there a way to build such environment without a verification tool?