I am Trying to use a bit_bash_sequence for my Register Checking.
Is it possible to use it for Read Only Registers. Right now I am seeing an error that my DUT value does not match with mirrored value. Since its a Read Only Register the DUT bits are always Default Value (0x00) and the mirrored value are the value my sequence writes.
Is it possible to use this for my Read only Registers ?
Well I have another scenario that where my 8 bit RW registers have certain bits as RESERVED(Let’s say 3:0] . How do i get my bit bash sequence to ignore check on these CONST Reserved bits and do RW check on the remaining bits.
In reply to priyansh.ag:
The UVM’s bit bash sequence is not smart enough to deal with that. You’ll have to roll your own.
In reply to dave_59:
In reply to priyansh.ag:
The UVM’s bit bash sequence is not smart enough to deal with that. You’ll have to roll your own.
Is uvm bit bash sequence smart enough to handle only read-write access registers only. As am observing that for read only registers , it writing to them and then test are failing with UVM_NOT_OK response.
Anyone face this issue?
In reply to yuvraj khare:
This is not an issue. It reflects the real behavior. A RO register cannot be written using the write command. This results in an error.
If you want to do this you have to use instead of the write the poke, which is a backdoor write. This is legal.
But you should think about if a bit bash sequence is useful for RO registers.
In reply to chr_sue:
In reply to yuvraj khare:
This is not an issue. It reflects the real behavior. A RO register cannot be written using the write command. This results in an error.
If you want to do this you have to use instead of the write the poke, which is a backdoor write. This is legal.
But you should think about if a bit bash sequence is useful for RO registers.
I don’t want to write RO register, but look like this sequence is writing an RO register and this result an error.
Ideally this sequence should not write the RO registers.
In reply to yuvraj khare:
But the bit bash sequence tries to write the RO registers. Because this write is not successfull the expected register value and the actual value are different resulting in a compare error.
If you want to use the bit bash sequence you have to exclude the RO registers.
In reply to yuvraj khare:
In reply to chr_sue:
Yes got it.
Thanks
One more question regarding mirror task define in uvm ral , Is mirror task is valid for RO registers?
In reply to yuvraj khare:
In reply to yuvraj khare:
One more question regarding mirror task define in uvm ral , Is mirror task is valid for RO registers?
I am facing the issue, as am seeing the read data is coming correctly at BUS and same read data is coming at uvm_reg.svh also. But when am initiating the mirror task and read the same register, am getting an mis-match with DUT and mirrored value.
In reply to yuvraj khare:
The mirror command reads the DUT register only. The read command makes amirror and a get.
The get returns the value of the TB registers.
A read is doing a mirror followd by a get.
In reply to chr_sue:
In reply to yuvraj khare:
The mirror command reads the DUT register only. The read command makes amirror and a get.
The get returns the value of the TB registers.
A read is doing a mirror followd by a get.
When am using the read task, it gives me correct data from design from RO register. But when using mirror task, it throw an error.
Is mirror value is same as what we have write into that register? As this register is RO, so 'h0 has been written into the register and that is the mirror value.
In reply to yuvraj khare:
Are you sure your RAL is modelled correctly?
BTW I have to correct myself. Above I wrote the RAL RO register will be written. This is incorrect.
Could you please show Your simulation log-file showing the write to the RO register and the read as well as the mirror.
In reply to chr_sue:
Issue resolved. When you write into RO registers with non-zero value, and compare the mirrored value, it will fail if registers have default value non-zero.
We need to exclude the checker for RO registers.
In reply to chr_sue:
Did you know, how to exclude the RO registers. I know,use the uvm_resource_db set(), but there are around 1000 read only registers, so it very cumbersome task.
Is there anyother way to do this!
In reply to yuvraj khare:
The function ‘get_rights’ returns the actual access. You can check like this
if (data_regs[i].get_rights() != "RO")
where data_regs is the list of all registers.