Binding interface to dut in top

UVM
,
1

Hi,

Please find my code on the edaplayground here: Basic sequencer-driver connection - EDA Playground

In the top module, I am instantiating the dut and then am trying to bind an interface to the signals on it.

module tb_top;
  dut dut1();
  bind dut basic basic_intf(.clk(clk), .reset(reset), .addr(addr), .addr_out(addr_out));
  initial begin
    run_test("base_test");
  end  
endmodule

interface basic(
  input clk,
  input reset,
  inout [7:0] addr,
  inout [7:0] addr_out);
  
  modport dut(
    input clk,
    input reset, 
    input addr,
    output addr_out
  );
endinterface

The error I am getting is:

Error-[VIHIOP] Variable in high conn of inout port
testbench.sv, 144
dut, “clk”
This variable is not a net, it cannot be connected to an inout port.
Source info: : basic basic_intf( .clk (clk), .reset (reset), .addr (addr),
.addr_out (addr_out));

If I declare these signals as wire I will not be able to use <= operator in the driving function. I want add that interface to config_db and retrieve it in the test. Test is a class of type uvm_test.

How do I resolve this?