Hi,
I have a vector, logic [X-1:0]CHILD_SIG. I need to add a check in UVM monitor class such that each bit of this vector make 0->1 and 1->0 transitions in a particular sequence (e.g: bit0_transition_to_1 → bit5_transition_to_1 → bit3_transition_to_0), else flag an error. Apart from checking, I would also like to create a packet describing the sequence to pass to coverage class etc. What is the best/scalable of realizing this?
Why scalability because, later, I would have several of these vectors: CHILD_SIG0, CHILD_SIG1… CHILD_SIG7 and also a logic[Y-1:0]PARENT_SIG. In PARENT_SIG monitor or somewhere above its hierarchy, I need packets which describe transitions like :
child0_bit0_transition_to_1 → child3_bit0_transition_to_1 → parent_bit8_transition_to_0 and so on.
I’m not looking for exact SV code, but data-type/code placement strategy for realizing this.
Thank you in advance!
Rishi
In reply to rishikpillai90:
The ideal place to put this would be inside the interface connected to your monitor class as an assertion (SVA). Assertions provide a powerful syntax to perform these kind of temporal checks. Plus they simultaneously give you the coverage information you are looking for.
Transition coverage in a covergroup was only designed to handle transitions of a single piece of data. You could try concatenating these signals together and looking for transitions as a vector. However, covergroups are great for checking when something passes - it’s much harder to capture failures with illegal_bins, plus you cannot generate uvm_errors when it does fail.
In reply to dave_59:
Hi Dave,
If I have many such similar vectors (CHILD_SIG0, CHILD_SIG1 etc. as described in my original post) which are already part of separate instances of same interface, checking for transition sequence across them cannot be done by SVA inside a single interface, correct?
Also, I feel that if I concatenate all these vectors into a single one as you described, the solution becomes very much dependent on number of vectors I have. And the assertions might look cumbersome if the number of vectors to be concatenated increases in a later project.
I could put the SVA related to individual vector in the interface, and for cross-transitions, I thought of pushing the transition information into a queue as they happen, and passing the queue into an upstream checker when one sequence complete. The checker could re-arrange the information from different such monitors and create a bigger single queue.
In reply to rishikpillai90:
Using the bind construct, you can connect an interface to many different singles in different parts of your hierarchy.
The concatination is the only way of collecting transition coverage between multiple signals. It probably won’t work for you. Your checker will probably have to implement a state machine to collect all the transitions.