In reply to chr_sue:
In reply to uvmsd:
A certain number of clock cycles can be also such an indication.
I could come up with certain number of clocks to introduce delay in driver. Looks like i am kind of stuck with the monitor now.
Here are the thigs to follow for my TB:
1. Write into RAM1 (800 bytes):
**** I generated sequences with wr_addr, wr_en, wr_data
2. Trigger a control module which reads data from the above RAM1, writes into another similar RAM2 (with huge interleaved delays)
**** I generated sequences t set/reset the trigger bit
**** based on the above trigger bit, I waited for a certain delay in the Driver
3. Read the RAM2 and check the data integrity.
I have just started working on Monitor. Since there is a clk delay to read RAM2, i need to add 1 clk delay to get rd_data, without affecting inputs capture.
I am thinking something like below:
virtual task run_phase(uvm_phase phase);
// capture the RAM1 write inputs
if(vif.trigger) begin //for the control_module
//wait for [b]certain delay[/b]
delay_done = '1;
if(mon_items.size() > 0) begin
seq_item seq_item_collected = mon_items.pop_front();
if(seq_item_collected.ram1_wr == 1 || delay_done)
Its a rough code that i have thought.
1. With above approach, i am apprehensive if all the certain delays(driver, monitor) would match and the sequences would occur as expected. And also the read to RAM2(rd_addr,rd_data) are placed at right time.
2. Other way is sending an uvm_event from driver when actual read_addr are placed for RAM2 so that, driver and monitor are in sync.
3.Add a control bit in seq_item, just to indicate its a read to RAM2. This can be used in monitor to sample the rd_data from RAM2. This is more clear than other two options. But is it good practice to add a bit in seq_item just for TB use?
I have just started working on UVM TBs and don't have any UVM code, guidelines or anyone who knows UVM at work.
Just get thinking about the options. Please guide.