Best method to write sequences

UVM
,
1

Hi,

I am verifying Bluetooth 5.0 and I would like to know the best method of writing layered sequences keeping controllability and reusability in mind.

FIRST APPROACH:

There is a virtual sequence which I haven’t shown here and the mid level_1 sequence is as follows:

class ble_set_adv_ext_parameters extends uvm_sequence;

	task body();	
		
		set_conn_idx_seq.start(m_sequencer,this);		
		set_adv_param_seq.start(m_sequencer,this);	
		
	endtask
	
endclass

The mid level_2 sequence is as follows:

class ble_set_connection_index_sequence extends uvm_sequence;

	task body();
	
		ble_ahb_sing_wrt_seq =  ble_ahb_single_write_sequence :: type_id :: create("ble_ahb_sing_wrt_seq");
		
		ble_ahb_sing_wrt_seq.write(32'h0 , 16'h0,m_sequencer,this);
		
	endtask
	
endclass

Then there is a bottom level sequence :

class ble_ahb_single_write_sequence extends uvm_sequence #(ble_ahb_sequence_item);	
	
	extern task body();
	
	extern task write(input bit [31:0] haddr, input bit[15:0] hwdata,input uvm_sequencer_base seqr,input uvm_sequence_base parent = null);
	
endclass
task ble_ahb_single_write_sequence :: body();
	
	start_item(ble_ahb_seq_item);

		assert (ble_ahb_seq_item.randomize() with {														
                                                            ble_ahb_seq_item.haddr == local :: haddr;
						            ble_ahb_seq_item.hwdata == local :: hwdata;
							    ble_ahb_seq_item.hwrite == 1;
							    ble_ahb_seq_item.hsel   == 1;
							    ble_ahb_seq_item.hburst == 3'b000;
													  });												  
		
	finish_item(ble_ahb_seq_item);
	
	`uvm_info("AHB_Single_Write_Sequence", "Exiting Slave Sequence", UVM_LOW)
	
endtask

task ble_ahb_single_write_sequence :: write (input bit [31:0] haddr, input bit[15:0] hwdata,input uvm_sequencer_base seqr,input uvm_sequence_base parent = null);

	this.haddr = haddr;
	this.hwdata = hwdata;
	this.start(seqr,parent);
	
endtask

SECOND APPROACH:
In this approach, the mid_level sequence is not sub-divided

class ble_set_adv_ext_parameters extends uvm_sequence;

	task body();	
		
		ble_ahb_sing_wrt_seq.write(32'h0 , 16'h0,m_sequencer,this);
		ble_ahb_sing_wrt_seq.write(32'h5 , 16'h456,m_sequencer,this);
		
	endtask
	
endclass

If I want to change the data written into the registers, and if I follow the first approach, I can override only the required mid_level_2 sequence without changing the mid_level_1 sequence. However if I use the second approach, If I want to change the written data, I have to use a new mid_level_1 sequence.

2

In reply to PK:

It would be good if you could explain what your objective si and why you are going this way. In my eyes this has nothing todo with layered sequences. It looks like you are working with virtual seqúences.
I do not see what your m_sequencer is.