Behavior between inter-dependent registers inside UVM Register Model ? How to Solve it out?

UVM
1

Hello All,

Have a scenario for UVM register model as given below.

a. Say there are 5 registers {a, b, c, d, e} inside the DUT and the UVM register model is created for the same.
b. But there is a catch/interlink between register b and c i.e. if I write “1” to a bit in the register “b”, that internally would clear the corresponding bit in the register “c”.
c. And similarly if I write “1” to a bit in register “c”, then that would set the corresponding bit in register “b”.

How do I take care of such scenarios inside UVM register model ? Do I need to play with some user-defined access type callbacks ?

Share in your comments, ideas, thought process !!

Thanks,
Desperado

2

In reply to desperadorocks:

Hello Engineers !!!

Any Comments ? Suggestions ? Etc ???

Drop in your thought process !!

Thanks In Adv !!
Desperado

3

I have a similar question. How would one define interdependency between registers? If two registers need to be mapped to one flop on the rtl, how it that defined while performing backdoor access?

For example : uvm reg a,b rtl flop x_p.
How do you add hdl path to the registers a,b for backdoor access when they’re both linked to one flop x_p? Can I add the same path to both registers?