BAD HANDLE OR REFERENCE ERROR

Hi,

I am getting error like Fatal: (SIGSEGV) Bad handle or reference, after implementing `uvm_analysis_imp_decl in scoreboard. I dont know if the issue is because of this or some other thing in my TB. The flow stops after entering monitor and I get Fatal Error.

Thanks

In reply to sujay_rm:

Could you please some code around your problem.

In reply to chr_sue:

Here’s my monitor code:

class uart_wr_mon extends uvm_monitor;
uart_wr_tx wtx;
virtual uart_if vif;
uvm_analysis_port#(uart_wr_tx) wr_item_collected_port;
`uvm_component_utils(uart_wr_mon)

function new(string name="uart_wr_mon", uvm_component parent);
	super.new(name,parent);
	wr_item_collected_port=new("wr_item_collected_port",this);
endfunction

function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	if(!uvm_config_db#(virtual uart_if)::get(this,"*","vif",vif))
		`uvm_error("NO_VIF","Virtual Interface is not set for monitor")
endfunction

task run_phase(uvm_phase phase);
forever begin
	monitor_logic();
end
endtask

task monitor_logic();
	$display("Entered into MONITOR");
	@(vif.wb_clk_i);
	wait(vif.wb_ack_o);
	wtx.wb_stb_i = vif.wb_stb_i;
	wtx.wb_cyc_i = vif.wb_cyc_i;
	wtx.wb_adr_i = vif.wb_adr_i;
	wtx.wb_dat_i = vif.wb_dat_i;
	wtx.wb_we_i = vif.wb_we_i;

	if((wtx.wb_adr_i==0) && (wtx.wb_we_i==0) && (wtx.lcr[7]==0)) begin
		wtx.rbr.push_back(vif.wb_dat_o);
	end

	if((wtx.wb_adr_i==0) && (wtx.wb_we_i==1) && (wtx.lcr[7]==0)) begin
		wtx.thr.push_back(vif.wb_dat_i);
	end
	if((wtx.wb_adr_i==1) && (wtx.wb_we_i==1)) begin
		wtx.ier <= vif.wb_dat_i;
	end
	if((wtx.wb_adr_i==2) && (wtx.wb_we_i==0)) begin
		wtx.iir <= vif.wb_dat_i;
	end
	if((wtx.wb_adr_i==2) && (wtx.wb_we_i==1)) begin
		wtx.fcr <= vif.wb_dat_i;
	end
	if((wtx.wb_adr_i==3) && (wtx.wb_we_i==1)) begin
		wtx.lcr <= vif.wr_mon_cb.wb_dat_i;
	end
	if((wtx.wb_adr_i==4) && (wtx.wb_we_i==1)) begin
		wtx.mcr <= vif.wr_mon_cb.wb_dat_i;
	end
	if((wtx.wb_adr_i==5) && (wtx.wb_we_i==0)) begin
		wtx.lsr <= vif.wr_mon_cb.wb_dat_i;
	end
	if((wtx.wb_adr_i==6) && (wtx.wb_we_i==0)) begin
		wtx.msr <= vif.wr_mon_cb.wb_dat_i;
	end
	if((wtx.wb_adr_i==0) && (wtx.wb_we_i==1) && (wtx.lcr[7]==1)) begin
		wtx.dlb1 <= vif.wr_mon_cb.wb_dat_i;
	end
	if((wtx.wb_adr_i==1) && (wtx.wb_we_i==1) && (wtx.lcr[7]==1)) begin
		wtx.dlb2 <= vif.wr_mon_cb.wb_dat_i;
	end
	wr_item_collected_port.write(wtx);
endtask

endclass

In reply to chr_sue:

Here’s my scoreboard

uvm_analysis_imp_decl(_wr_mon) uvm_analysis_imp_decl(_rd_mon)
class uart_sbd extends uvm_scoreboard;

`uvm_component_utils(uart_sbd)
uvm_analysis_imp_wr_mon#(uart_wr_tx,uart_sbd) wr_item_collected_export;
uvm_analysis_imp_rd_mon#(uart_rd_tx,uart_sbd) rd_item_collected_export;
uart_wr_tx wtx;
uart_rd_tx rtx;

int uart1tx[$];
int uart1rx[$];
int uart2tx[$];
int uart2rx[$];

function new(string name="uart_sbd",uvm_component parent);
	super.new(name,parent);
endfunction	

function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	wr_item_collected_export = new("wr_item_collected_export", this);
	rd_item_collected_export = new("rd_item_collected_export", this);
endfunction

function void write_wr_mon(uart_wr_tx wtx);
	$display("SBD:: Write Tx Recieved");
	wtx.print();
endfunction	

function void write_rd_mon(uart_rd_tx rtx);
	$display("SBD:: Read Tx Recieved");
	rtx.print();
endfunction	

function void check_phase(uvm_phase phase);
	compare();
endfunction

function void compare();
	uart1tx.push_back(wtx.wb_dat_i);
	uart1rx.push_back(wtx.wb_dat_o);
	uart2tx.push_back(rtx.wb_dat_i);
	uart2rx.push_back(rtx.wb_dat_o);

	if((uart1tx==uart2rx) && (uart2tx==uart1rx))
		$display("DATA MATCH SUCCESSFUL");
	else
		$display("DATA MATCH NOT SUCCESSFUL");


endfunction

endclass

uvm_analysis_imp_wr_mon#(uart_wr_tx,uart_sbd) wr_item_collected_export;
uvm_analysis_imp_rd_mon#(uart_rd_tx,uart_sbd) rd_item_collected_export;

here you are parameterizing uvm_analysis_imp_wr_mon,uvm_analysis_imp_rd_mon with the transaction class than you need to import wr_transaction,rd_transaction also in scoreboard class .

In reply to hurmath@fldec:
I have already included these classes in scoreboard, check 7th and 8th line of the code.

uart_wr_tx wtx;
uart_rd_tx rtx;

this is handle decleration sir ,

you need to include like that:

include"uart_wr_tx.sv" include"uart_rd_tx.sv"

In reply to hurmath@fldec:

All include files are in the package class and the order is also correct

Have you created object wtx in monitor ?

In reply to chiragm:

Yes I have created.

In reply to sujay_rm:

As was asked before, your code does not show ‘wtx’ being created anywhere. If your code isn’t accurate, then we can’t help you.

I would expect to see in the task monitor_logic():


wtx = uart_wr_tx::type_id::create("wtx");