Hi,
This is about UVM RAL. If I use backdoor write access to a read-only register, will it be written?
I ask this because if backdoor access uses assign or force statements to access the registers, then read-only registers can be written.
Can someone help me to understand backdoor access correctly?
Thank you.
Regards,
Reuben
In reply to Reuben:
If your reg is “RO” and you aim to write to it, you will get a UVM_ERROR and write will not occur. It does not matter if you are doing a backdoor or a frontdoor write.
Ahmed
In reply to ayehia:
Hi Ahmed,
Thanks for the reply.
But if the purpose of the verification is to test the RO access of the register, this should not be a UVM_ERROR. Am I right? UVM should allow error cases to verify scenarios like this.
UVM_ERROR should only flag if after writing to RO register the data has been written on it.
Regards,
Reuben
In reply to Reuben:
Looks like I was totally missing the point of the question here, so apologies I stand corrected. The issue I was referring to, was about multiple registers mapped to the same address with different access rights (sometimes this is needed), then in this case callbacks are activated which will trigger errors in case you did a write for an RO version of a register.
Now back to your question about regular “RO” registers. Backdoor reads (e.g. via peek) should be OK, they should read the register and update the shadow/main and mirror registers.
You can also use a backdoor (via UVM PLI) write (e.g. via poke), only glitch if the DUT is continuously updating the register, its value would be changed in the next cycle, at this moment you will have different main/mirror vs. DUT versions of the register so you need to accommodate for that. Regular testing is also valid (e.g. FD writes, FD/BD reads).
Hope this helps!
Ahmed
In reply to Reuben:
Hi,
If you are using irun, then we can do backdoor write access to RO registers using $ncdeposit
Regards,
Santosh.Vangala