Backdoor write is not working, if questa tool problem what is the commands need for backdoor to work?

UVM
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1

I am trying to do a backdoor write, In the sim.log it says registers are specified in the force but the write is not happening.
Eg.
UVM_INFO /eda/dm/home/skotareddy/jhr3021/v1a/digital/chip/verif/seq/backdoor_sanity_seq.sv(76) @ 1944225420: uvm_test_top.chip_env.agent.i2c_sqr@@bck_dr_seq [backdoor_test_seq] *****************Performing backdoor write of 8’hab to hardware register ****************************

** Warning: (vsim-8780) Forcing /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/rm_tapirqen as root of /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/i_reg_map_top/i_reg_map/rm_tapirqen specified in the force.

** Warning: (vsim-8780) Forcing /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/rm_closeirqen as root of /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/i_reg_map_top/i_reg_map/rm_closeirqen specified in the force.

** Warning: (vsim-8780) Forcing /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/rm_farirqen as root of /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/i_reg_map_top/i_reg_map/rm_farirqen specified in the force.

** Warning: (vsim-8780) Forcing /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/rm_compdoneirqen as root of /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/i_reg_map_top/i_reg_map/rm_compdoneirqen specified in the force.

** Warning: (vsim-8780) Forcing /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/rm_capconvdoneirqen as root of /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/i_reg_map_top/i_reg_map/rm_capconvdoneirqen specified in the force.

** Warning: (vsim-8780) Forcing /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/rm_hallsatirqen as root of /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/i_reg_map_top/i_reg_map/rm_hallsatirqen specified in the force.

** Warning: (vsim-8780) Forcing /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/rm_hallconvdoneirqen as root of /chip_tb/dut_wrapper/DUT/Ijhr3021_dig/i_reg_map_top/i_reg_map/rm_hallconvdoneirqen specified in the force.

HDL path for the fields in the registers is correct, I ran an inbuilt uvm sequence to check the hdl path correctness. Is there any command that is associated with Questa or in the Make file that needs to be included that makes backdoor work?
Note: backdoor read is working fine
Code for backdoor


class backdoor_sanity_seq extends chip_prog_base_seq;
  `uvm_object_utils(backdoor_sanity_seq)
  
 function new(string name = "");
    super.new(name);
  endfunction: new
  
  
  virtual task body();      
  bit[7:0] value;
  string paths[$];
  uvm_hdl_path_concat pathc[$];

  super.body();

  


 /******************************************************************************************************************/
 /*

		TESTING HARDWARE REGISTER (COMBINATIONS OF BACKDOOR AND FRONT DOOR)


														  */
 /******************************************************************************************************************/




 /************************************* ACCESS : RW ****************************************************************/


  `uvm_info("backdoor_sanity_seq", $sformatf("*****************Performing front write of 8'h15 to hardware register ****************************"), UVM_LOW)
   reg_model.REG_IRQMSK.write(status, 8'h15);
  // `uvm_info("backdoor_sanity_seq", $sformatf("desired=0x%0h mirrored=0x%0h" , reg_model.REG_IRQMSK.get(), reg_model.REG_IRQMSK.get_mirrored_value()),UVM_LOW)
   assert( status == UVM_IS_OK );
  
  `uvm_info("backdoor_sanity_seq", $sformatf("*****************Performing backdoor read to hardware register ***************************"), UVM_LOW)
   reg_model.REG_IRQMSK.read(status, value, UVM_BACKDOOR); 
   //`uvm_info("backdoor_sanity_seq", $sformatf("desired=0x%0h mirrored=0x%0h" , reg_model.REG_IRQMSK.get(), reg_model.REG_IRQMSK.get_mirrored_value()),UVM_LOW)
   `uvm_info("backdoor_sanity_seq", $sformatf("register readback value is :%h ", value),UVM_LOW)
   assert( status == UVM_IS_OK );
   if(value  != 8'h15) begin
     `uvm_error("backdoor_test_seq", "backdoor sequence is not working") 
   end

 /************************************* ACCESS : RW ****************************************************************/


  `uvm_info("backdoor_test_seq", $sformatf("*****************Performing backdoor write of 8'hab to hardware register ****************************"), UVM_LOW)
   reg_model.REG_IRQMSK.write(status, 1'b1, UVM_BACKDOOR);
  // `uvm_info("backdoor_sanity_seq", $sformatf("desired=0x%0h mirrored=0x%0h" , reg_model.REG_IRQMSK.get(), reg_model.REG_IRQMSK.get_mirrored_value()),UVM_LOW)
   assert( status == UVM_IS_OK );
  
  `uvm_info("backdoor_sanity_seq", $sformatf("*****************Performing frontdoor read to hardware register***************************"), UVM_LOW)
   reg_model.REG_IRQMSK.read(status, value); 
   `uvm_info("backdoor_sanity_seq", $sformatf("register readback value is :%h ", value),UVM_LOW)
  // `uvm_info("backdoor_sanity_seq", $sformatf("desired=0x%0h mirrored=0x%0h" , reg_model.REG_IRQMSK.get(), reg_model.REG_IRQMSK.get_mirrored_value()),UVM_LOW)

   assert( status == UVM_IS_OK );
   if(value  != 8'hab) begin
     `uvm_error("backdoor_sanity_seq", "backdoor sequence is not working") 
   end


/******************************************************************************************************************/
/*

		TESTING SOFTWARE REGISTERs (COMBINATIONS OF BACKDOOR AND FRONT DOOR)


														  */
/******************************************************************************************************************/

/*********************************Frontdoor Write and Backdoor Read ********************************************************************************/  
   
  `uvm_info("backdoor_sanity_seq", $sformatf("Performing frontdoor write (8'b11_101111) to software register "), UVM_LOW)
   reg_model.RAM_PROXUSEFULMSB_PH2.write(status, 8'b11_101111);
   assert( status == UVM_IS_OK );

   `uvm_info("backdoor_sanity_seq", $sformatf("Performing backdoor read to software register"), UVM_LOW)
   reg_model.RAM_PROXUSEFULMSB_PH2.read(status, value, UVM_BACKDOOR); 
    `uvm_info("backdoor_sanity_seq", $sformatf("register readback value is :%b ", value),UVM_LOW)
   assert( status == UVM_IS_OK );
   if(value  != 8'b11_101111) begin
     `uvm_error("backdoor_test_seq", "backdoor sequence is not working") 
   end

/*********************************Backdoor Write and Frontdoor Read ********************************************************************************/  
   
  `uvm_info("backdoor_sanity_seq", $sformatf("Performing backdoor write(8'b11_101_001)) to software register"), UVM_LOW)
   reg_model.RAM_VECTORMAG_PARAM.poke(status, 8'b11_101_001, .parent(this));
   assert( status == UVM_IS_OK );

   `uvm_info("backdoor_sanity_seq", $sformatf("Performing frontdoor read to software register"), UVM_LOW)
   reg_model.RAM_VECTORMAG_PARAM.read(status, value); 
    `uvm_info("backdoor_sanity_seq", $sformatf("register readback value is :%b ", value),UVM_LOW)
    //`uvm_info("backdoor_sanity_seq", $sformatf("desired=0x%0h mirrored=0x%0h" , reg_model.RAM_VECTORMAG_PARAM.get(), reg_model.RAM_VECTORMAG_PARAM.get_mirrored_value()),UVM_LOW)
   assert( status == UVM_IS_OK ); 
   if(value  != 8'b11_101_001) begin
     `uvm_error("backdoor_sanity_seq", "backdoor sequence is not working") 
   end



  endtask :body
  
  endclass:backdoor_sanity_seq

`endif
2

In reply to sumanth291092:

I would also run the built-in register access checks to see if there is anything wrong with your sequences.

Regarding tool specific read and write access, this Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please read your tool’s user manual or contact your tool vendor directly for support.