Backdoor Register Layer Access

UVM
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1

Hello,

I am trying to write some value to through backdoor access to register cnt_reg in my vhdl design.

 process (clk, reset, rw)
  begin
      if reset = '1' then
         cnt_reg <= (others => '0');
      elsif clk'event and clk = '1' then
         if(rw = '1') then
            cnt_reg <= cnt_reg + '1';
         end if;
      end if;
  end process;

I am introducing myself to UVM register layer so design is very simple, anyway when i try this in test:
m_env.m_agent.m_reg_block_p1.cntrl_reg.write(status, 'b101, UVM_BACKDOOR);
it writes 101 but in HEX notation, like 0001 0000 0001,
if i simply try to write
m_env.m_agent.m_reg_block_p1.cntrl_reg.write(status, 23, UVM_BACKDOOR);
i see 32’h0001 0111 (this is hex).
I cant figure it out why he take binary number and represent it in same way but in hex.

this is build phase of my agent :

function void build_phase(uvm_phase phase);
   m_driver       = driver::type_id::create("m_driver",this);
   m_sequencer    = command_sequencer::type_id::create("m_sequencer", this);
   m_monitor 	   = monitor::type_id::create("m_monitor", this);
   m_reg_adapter 	= reg_adapter::type_id::create("m_reg_adapter", this);
  **m_reg_block_p1 = reg_block_p1::type_id::create("m_reg_block_p1", this);
   m_reg_block_p1.configure(.hdl_path("top.dut"));
   m_reg_block_p1.build();
   m_reg_block_p1.cntrl_reg.clear_hdl_path();
   m_reg_block_p1.cntrl_reg.add_hdl_path_slice( .name( "cnt_reg" ), .offset( 0 ), .size( 8 ) );
   m_reg_block_p1.lock_model();**
endfunction : build_phase

This is register block:

class reg_block_p1 extends uvm_reg_block;
   `uvm_object_utils(reg_block_p1)
 
   rand reg_cntrl_rw cntrl_reg;
   uvm_reg_map       reg_map;
 
   function new( string name = "reg_block_p1" );
      super.new( .name( name ), .has_coverage( UVM_NO_COVERAGE ) );
   endfunction: new
 
   virtual function void build();
      cntrl_reg = reg_cntrl_rw::type_id::create("cntrl_reg");
      cntrl_reg.configure( .blk_parent( this ), .hdl_path("reg_mod") );
      cntrl_reg.build();

      reg_map = create_map(.name("reg_map"), 
                           .base_addr(8'h00), 
                           .n_bytes(1), 
                           .endian(UVM_LITTLE_ENDIAN));

      reg_map.add_reg(.rg(cntrl_reg),
                      .offset(8'h00),
                      .rights("RW"));      
   endfunction: build

I have one more question. I am not sure if my hdl paths are correct. For example what should i put as hdl path when i configure register? is this correct?
cntrl_reg.configure( .blk_parent( this ), .hdl_path(“reg_mod”) );
reg_mod is name of my vhdl entity.

But in top module i have this:

reg_mod  dut(    .data_in(dut_interface.data_in), .addr(dut_interface.addr), 
                 .rw(dut_interface.rw), .clk(dut_interface.clk), 
                 .reset(dut_interface.reset), .result(dut_interface.result));

endclass: reg_block_p1
2

In reply to Sanjin_Arsenovic:

sorry about indentations, i am not sure why are they missing i didnt post like this.

3

In reply to Sanjin_Arsenovic:

Please use code tags. I have added them for you.

4

In reply to Sanjin_Arsenovic:

You are setting some hdl_path and call then clear_hdl_path:

   m_reg_block_p1.configure(.hdl_path("top.dut"));
   m_reg_block_p1.build();
   m_reg_block_p1.cntrl_reg.clear_hdl_path();

I’d recommend you should call add_hdl_path in your register model.
To check whether a hdl path does exist or not you can call uvm_hdl_check_pth.

5

In reply to chr_sue:
If i try to put

m_reg_block_p1.cntrl_reg.clear_hdl_path();

before

m_reg_block_p1.configure(.hdl_path("top.dut"));

it gives me fatal error

and if i omit

m_reg_block_p1.cntrl_reg.clear_hdl_path();

it gives me fatal error, so i guess its there for a reson.
But i think all paths are ok, because i can write to specific register. Problem is that when i write :
'b0101 it writes : 'h0101 == 'b0000_0001_0000_0001
It does that for every value that i try to write.
I cant locate problem.

6

In reply to Sanjin_Arsenovic:

Maybe there is your problem, with clearing the hdl_path. Finally there is no reason to do this and again I’m recommending to do add_hdl_path() in the reg model.