I had some issues with uvm_hdl_force. Below a description of the steps I took.
The signal I want to force, is an output signal of a VHDL entity in our design. The entity was defined with a component. We have two architectures for this entity and the correct architecture was selected using a configuration.
The VHDL component is used somewhere deep within our verilog modules.
The testbench is a System Verilog module which calls the UVM-framework (run_test()).
I used uvm_hdl_check_path, to check the path was valid. It always returned 1, while it returns 0 if I enter a non existing path. I assume the path was ok.
The path I entered….
tb_top_fwlta_rtl.dut.inst_fmi_top.inst_fmi_ctrl_dev.inst_fmi.C0_app_rd_data[0]
When I force this signal, uvm_hdl_force returns 0 and I get next error:
UVM_ERROR: set: unable to locate hdl path (tb_top_fwlta_rtl.dut.inst_fmi_top.inst_fmi_ctrl_dev.inst_fmi.C0_app_rd_data[0])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
I also tried to force this signal without specifying the index:
tb_top_fwlta_rtl.dut.inst_fmi_top.inst_fmi_ctrl_dev.inst_fmi.C0_app_rd_data
In this case, uvm_hdl_force returns 1. I didn’t get an error, but it did not force the signal….
I tried to run vsim with the –novopt option, but this gave no improvement.