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Backdoor access to Indirect registers

UVM 5528
kartavya
kartavya
Full Access
24 posts
November 20, 2020 at 10:46 am

I have a register which can be accessed through indirect mechanism only.
Below is the example (copied from another forum)

/ -----------------------------------------
// Real DUT register
// way field controls which data register
// will be ascessed
// ------------------------------------------
class ctrl_reg extends uvm_reg;
  uvm_reg_field   some_field;
  uvm_reg_field  way; // if 0, access to data0 reg, if 1, access to data1 reg
endclass
 
// -----------------------------------------
// Virtual register, idx field is a handle
// to way field of ctrl_reg
// ------------------------------------------
class idx_reg extends uvm_reg;
  uvm_reg_field   idx;
endclass
 
// -----------------------------------------
// data0 and data1 share the same physical
// address
// ------------------------------------------
class data0_reg extends uvm_reg;
  uvm_reg_field field0;
endclass
 
class data1_reg extends uvm_reg;
  uvm_reg_field field0;
  uvm_reg_field field1;
endclass
 
// -----------------------------------------
// Indirect register for accesing data0 and
// data1 registers.
// The number of bits in each register in 
// the register array must be equal to n_bits 
// of this register.
// ------------------------------------------
class data_reg extends uvm_reg_indirect_data;
// No fields
endclass
class reg_model extends uvm_reg_block;
  ctrl_reg  ctrl;
  idx_reg   idx;
  data0_reg data0;
  data1_reg data1;
  data_reg  data;
  uvm_reg   reg_ar[];
 
  virtual function build();
    reg_ar = new[2];
 
    data0 = data0_reg::type_id::create();
    data0.configure(this);
    data.build();
 
    data1 = data1_reg::type_id::create();
    data1.configure(this);
    data.build();   
 
    reg_ar[0] = data0;
    reg_ar[1] = data1;
 
    ctrl = ctrl_reg::type_id::create();
    ctrl.configure(this);
    ctrl.build();
 
    idx = idx_reg::type_id::create();
    idx.configure(this);
    idx.build();
 
    idx.idx = ctrl.way;
 
    data = data_reg::type_id::create();
    data.configure(idx, reg_ar, this, null);
    data.build();
 
    default_map = create_map(““, 0, 4, UVM_BIG_ENDIAN);
    default_map.add_reg(ctrl, 0);
    default_map.add_reg(data, 4);
 
  endfunction
 
  endclass

According to the userguide "The registers in the indirect register array cannot be accessed via a back-door access to the “data” register.
Back-door access to the register array is provided by performing back-door accesses via the unmapped,indirect register itself."
In that case,how should I access data0 and data1 backdoor.

Thanks

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