BACKDOOR access could not success

hi guys,

when i using Backdoor to write register and found that could not writing succeed. please help me guys, thanks. posted code below.
frontdoor read/write could be success, so used to check backdoor’s operation results.

class gpio_cfg_reg_seq extends uvm_reg_sequence;
`uvm_object_utils(gpio_cfg_reg_seq)
gpio_regfile reg_model;

function new(string name=“gpio_cfg_reg_seq”);
super.new(name);
endfunction : new

//`uvm_declare_p_sequencer(gpio_sequencer)
rand bit [31:0] data;
bit [31:0] rdata;
rand int gpio_inst;
string gpio_rf;

virtual task body();

 uvm_status_e status;
 uvm_reg_data_t data;

  **reg_model.direction_mode.write(status, 32'h5678, UVM_BACKDOOR, .parent(this));**     
  **reg_model.direction_mode.read(status, data, UVM_FRONTDOOR, .parent(this));** 

endtask

endclass : gpio_cfg_reg_seq

====================================================================================
class case_base extends uvm_test;

subsystem_config o_cfg;
subsystem_virtual_sequencer v_seqr;
subsystem_env o_env;

apb_ss_reg_model_c reg_model_ss; // Register Model
gpio_regfile reg_model;
reg_to_ahb_adapter reg2ahb; // Adapter Object - REG to APB
uvm_reg_predictor#(ahb_transfer) ahb_predictor; //Predictor - APB to REG

uvm_component_utils_begin(case_base) uvm_field_object(reg_model, UVM_DEFAULT | UVM_REFERENCE)
uvm_field_object(reg2ahb, UVM_DEFAULT | UVM_REFERENCE) uvm_component_utils_end

//function new(string name, uvm_component parent=null);
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
o_env = subsystem_env::type_id::create(“o_env”,this);
o_cfg = subsystem_config::type_id::create(“o_cfg”,this);
v_seqr = subsystem_virtual_sequencer::type_id::create(“v_seqr”,this);

ahb_predictor = uvm_reg_predictor#(ahb_transfer)::type_id::create("ahb_predictor", this);
reg2ahb = reg_to_ahb_adapter::type_id::create("reg2ahb");
reg_model_ss = apb_ss_reg_model_c::type_id::create("reg_model_ss",this);
reg_model = gpio_regfile::type_id::create("reg_model",this);
uvm_reg::include_coverage("*", UVM_CVR_ALL); 
reg_model.configure(null,"");

reg_model.build(); 
reg_model.lock_model();
reg_model.reset();
**reg_model.set_hdl_path_root("subsystem_top.i_apb_subsystem.i_gpio_veneer.i_gpio_lite.i_gpio_lite_subunit");**

uvm_config_db#(gpio_config)::set(null, "uvm_test_top.o_env.gpio0", "gpio_cfg", o_cfg.gpio_cfg);
uvm_config_db#(ahb_config)::set(null, "uvm_test_top.o_env.ahb0", "ahb_cfg", o_cfg.ahb_cfg);       //to be finish

if( reg_model != null) begin
   uvm_config_db#(gpio_regfile)::set(this, "v_seqr.subsystem_virtual_sequence.gpio_cfg_seq", "reg_model", reg_model); 
end

endfunction : build_phase

virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
//v_seqr.o_gpio_seqr = o_env.gpio0.g_agent.g_sequencer;
v_seqr.o_ahb_seqr = o_env.ahb0.master_agent.sequencer;

//reg_model.default_map.set_sequencer(o_env.ahb0.master_agent.sequencer, reg2ahb);
//reg_model.default_map.set_sequencer(o_env.gpio0.g_agent.g_sequencer, reg2ahb); 
reg_model.default_map.set_sequencer(v_seqr.o_ahb_seqr , reg2ahb);
reg_model.default_map.set_auto_predict(1);

//if (o_env.gpio0.g_agent.is_active == UVM_ACTIVE)  
//  v_seqr.o_gpio_seqr =  o_env.gpio0.g_agent.g_sequencer;

endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
//if(uvm_print_enabled == (UVM_HIGH))
o_cfg.print();
endfunction

task run_phase(uvm_phase phase);
super.run_phase(phase);
endtask

endclass

class gpio_regfile extends uvm_reg_block;
rand bypass_mode_c bypass_mode;
rand direction_mode_c direction_mode;
rand output_enable_c output_enable;
rand output_value_c output_value;
rand input_value_c input_value;
virtual function void build();
// Now create all registers
bypass_mode = bypass_mode_c::type_id::create(“bypass_mode”, , get_full_name());
direction_mode = direction_mode_c::type_id::create(“direction_mode”, , get_full_name());
output_enable = output_enable_c::type_id::create(“output_enable”, , get_full_name());
output_value = output_value_c::type_id::create(“output_value”, , get_full_name());
input_value = input_value_c::type_id::create(“input_value”, , get_full_name());
// Now build the registers. Set parent and hdl_paths
bypass_mode.configure(this, null, “bypass_mode”);
bypass_mode.build();
direction_mode.configure(this, null, “direction_mode”);
direction_mode.build();
output_enable.configure(this, null, “output_enable”);
output_enable.build();
output_value.configure(this, null, “output_value”);
output_value.build();
input_value.configure(this, null, “input_value”);
input_value.build();
// Now define address mappings
default_map = create_map(“default_map”, 0, 4, UVM_LITTLE_ENDIAN);
default_map.add_reg(bypass_mode, UVM_REG_ADDR_WIDTH'h00820000, "RW"); default_map.add_reg(direction_mode, UVM_REG_ADDR_WIDTH’h00820004, “RW”);
default_map.add_reg(output_enable, UVM_REG_ADDR_WIDTH'h00820008, "RW"); default_map.add_reg(output_value, UVM_REG_ADDR_WIDTH’h0082000c, “RW”);
default_map.add_reg(input_value, `UVM_REG_ADDR_WIDTH’h00820010, “RO”);
endfunction

`uvm_object_utils(gpio_regfile)

function new(input string name=“unnamed-gpio_rf”);
super.new(name, UVM_NO_COVERAGE);
endfunction : new

endclass : gpio_regfile

can anyone help me , thanks a lot.
posted log file below.

==============================================================

UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg.svh(2715) @ 200: reporter [RegMem] backdoor_read from %s subsystem_top.i_apb_subsystem.i_gpio_veneer.i_gpio_lite.i_gpio_lite_subunit.direction_mode

UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg.svh(2747) @ 200: reporter [RegMem] returned backdoor value 0x0

UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg.svh(2678) @ 200: reporter [RegMem] backdoor_write to subsystem_top.i_apb_subsystem.i_gpio_veneer.i_gpio_lite.i_gpio_lite_subunit.direction_mode

UVM_INFO @ 200: reporter [RegModel] Wrote register via DPI backdoor: reg_model.direction_mode=0x5678

UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_map.svh(1996) @ 30200: reporter [uvm_reg_map] Reading address 'h820004 via map “reg_model.default_map”…

UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg_map.svh(2044) @ 1450000: reporter [uvm_reg_map] Read 'h0 at 'h820004 via map “reg_model.default_map”: UVM_IS_OK…

UVM_INFO @ 1450000: reporter [RegModel] Read register via map reg_model.default_map: reg_model.direction_mode=0

============================================================================
result: write 0x5678, and reading but got 0x0000

In reply to hellolife:

The backdoor access needs the hdl_path. You have to set add_hdl_path and add_hdl_path_slice.

In reply to chr_sue:

thanks for your response…
by the way, how can I confirm the BACKDOOR read is success while using BACKDOOR writing.

below posted log file details.

UVM_INFO @ 90900000: reporter [RegModel] Wrote register via DPI backdoor: reg_model.direction_mode=0x5678

UVM_INFO verilog_src/uvm-1.1d/src/reg/uvm_reg.svh(2747) @ 180900000: reporter [RegMem] returned backdoor value 0x5678

UVM_INFO @ 180900000: reporter [RegModel] Read register via DPI backdoor: reg_model.direction_mode=5678

as we know that it’s impossible to catch data by waveform in BACKDOOR mode,Is the above simulation log is enough to confirm that BACKDOOR read(/write)is succeed? thanks.

posted sequence below;

reg_model.direction_mode.write(status, 32'h5678, **UVM_BACKDOOR**, .parent(this));     

reg_model.direction_mode.read(status, data, **UVM_BACKDOOR**, .parent(this));

In reply to hellolife:

Accessing the RAL works on the transaction level. You could define a corresponding transaction and display it oin the waveform. But waveform inspection is not the proper way to decide what is wrong and what is correct. This has to be done by compairing values/transaction automatically.
BTW for backdor acces I use the special methods peek and poke, only defined for backdoor.