AXI3 write transfer dependency

In AXI3 write transfer dependency, the BVALID is asserted after WVALID and WREADY got asserted, but there is no dependency between address channel and response channel. So, does it mean that write data channel can occur first and it will be accepted by the slave?
But, if that is the case than how write data is going to transfer to the slave side(BVALID becomes high) without even knowing the AWREADY and AWVALID. Can you please elaborate more on this dependency?

Please go through the link provided for more clarification of the question, page A3-41, Figure A3.6

http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf