AXI Interconnect in UVM

UVM
, , ,
1

I’m trying to develop AXI interconnect using UVM. I wanted to know the correct way to implement multiple masters and slaves to the same interconnect. Should I use multiple interface to connect individual master and slave to the interconnect? How can UVM help me in this? Also can I change the no. of interfaces in the simulation depending upon no. of master and slave. What will be the correct approach to do all of this ?

2

approch should be like that:-

The AXI protocol provides a single interface definition for describing interfaces

  1. between a master and the interconnect
  2. between a slave and the interconnect
  3. between a master and a slave.