cache-ability/Buffer-ability basically is a property of the interconnect/memory management unit which changes the characteristics of the transaction reaching the slave in terms of the data width, transaction size etc.
Ex: Two 16bit consecutive writes to a slave can be translated to one one 32 bit write at slave (First 16bit data & address will be buffered by the interconnect). Similarly, two consecutive 16-bit reads from master can translate only to a single 32-bit read from slave (32-bit read data and address will be cached by the interconnect).
In order to verify this, basically the same addr/read data cache, addr/write data buffer needs to be implemented in your end-to-end master slave AXI scoreboard of VIP (if you are planning to deliver one with your VIP). So, appropriate master/slave transaction comparison can be made instead of doing a regular one-to-one transaction comparisons which can result in false failure in such cases.
1) Care must be taken to flush/update the buffer/cache contents in the scoreboard based on the transactions generated by AXI master.
2) I have worked on cache-able/buffer-able for other processor protocol and verified the same. I believe the underlying concepts remains the same with AXI too, and any minor differences need to be taken care.