Assertion was not triggering

UVM
,
1

property loop_a;
@(posedge clk) disable iff(rst_n == 1’b1) ((a ==1’b1)&&(b==1’b0)&&(c==1’b0)|->[70:110]$rose(x) |-> [8:70]$fell(x);
endproperty

test calling 5 times in loop

@(posedge clk) disable iff(rst_n == 1’b1) ((a ==1’b1)&&(b==1’b0)&&(c==1’b0) this condition was satisfying 5 times,

but assertion was triggering only 4 times(last assertion trigger) instead of 5 times , can you please tell what is the reason

2

In reply to govind mualagapaka:

What dou you mean with ‘the assertion was triggering’?
Dou you mean the pre-condition was 5 times met?
How did you check this?