Assertion triggers on edge despite delay added

UVM
, , ,
1

Hi there, can you help me understand what is going on?


forever begin
   @(clk);
   #1ns;
   assert (X==Y) else 'uvm_error()
end

This is a snipped of my code. The values of x and y update on every edge of clk.

My expected behavior is that 1ns after every edge I’ll sample and compare the updated value of X and Y.

X is the desired value i expect to receive and Y comes from a probe in the DUT.

What I am getting instead is that the assertion triggers on every edge, randomly samples between either the pre-change or post-change value of both X and Y and then 1ns later I get the error message.

2

In reply to Azmo:

The statement ‘X=Y’ is an assignment. Do you mean ‘X==Y’?

3

In reply to Azmo:

Assertions (immediate and concurrent are always evaluated on edges. The delay does not matter.
And of course you are doing an assigment in the assertion and this does not make any sense because there is no return value.

4

In reply to chr_sue:

This is wrong. From the LRM:

Immediate assertions follow simulation event semantics for their execution and are executed like a statement in a procedural block. Immediate assertions are primarily intended to be used with simulation.

Since immediate assertions are executed in a procedural manner, the delay will certainly have an effect.

5

In reply to cgales:

Chuck, you are right. I have an example like this above which is showing this.

module top;
time t;
bit clk;

logic [2:0] req1; 
logic [2:0] req2; 
bit com;

always @(posedge clk)
 # 3
 if (com)
   assert (req1 === req2)
 else begin
   t = $time;
   #5 $error("assert failed at time %0t",t);
end

always #10 clk = ~clk;

initial begin
   com = 1'b1;
   clk = 1'b0;
   req1 = 3'b001;
   req2 = 3'b111;
end

endmodule