Assertion is failing

UVM
,
1

When top_hclk=1 , adcdig_en and adcanaen=1 then topsmpd_clk should be 1 and one clock before top_smps_pulse=1. also top_smps_pulse should be 0 for 3 clock cycles

My code is

property p1;
@(posedge hclk) 
(top_adcdigen==1 && top_adcanaen==1) |-> $rose(topsmpsd_clk) ##0 ($rose($past(top_smps_pulse,1));

endproperty

What is wrong in this code ? The assertion is failing.

Please find the waveform in below link

2

In reply to kulua:

Please use code tags making your code easier to read. I have added them for you.

It would also help if you made sure that all the identifiers in your description match the example code.

And finally the really big help would be creating a small testcase that generates the waveform with the assertion failing. That way we know exactly what you are expecting to pass.