((rose(rst))|-> (data == 4'h8) ##[1:] $stable(data)); ---- this code is not giving the offending error when data =9,
//(($rose(rstn))|-> always(data == 4’h8)); – This code is giving me syntax error for always keyword used.
Dealing with $ in an assertion is not a good coding style. Choose always a reasonable big number as I did (1000).
And you should think about if you can check this behavior together with other signals.
For the property above the simulator has to sample and to store a hugh amount of data which might slow down your simulation.
But this does not check the default value after the rst toggle, if default value is other than 16’hffff after the rst, then this won’t check that condition or give the error.
but is there any way to get properties in single property ?
as per Dave code as below, always is compiling in uvm, but not in normal SV simulation. is there any special packages in uvm to support always property in uvm ?
In reply to chr_sue:
But this does not check the default value after the rst toggle, if default value is other than 16’hffff after the rst, then this won’t check that condition or give the error.
That’s right.
It is not a bad coding style to split checking of a certain behavior into more than 1 property.
In contrast, you might get a better simulation behavior.
BTW the always solution is not compiling in my environment, using UVM 1.1d.
You are probably using an older version of a tool that does not support the always syntax. This has nothing to do with UVM if you are trying to write this inside an interface or module, not a class.