Assertion code to check the default value after reset and it should be stable till end of simulation

I want to code an assertion for default value after reset and it should be stable till end of simulation.

like ex:

property axi_wstrb_default;
            @(posedge clk) disable iff (!rst_n)
           (($rose(rst_n))|-> ((axi_acp_wstrb == 16'hffff) ##[1:$]($stable(axi_acp_wstrb))));
        endproperty

Can you please help me to write the correct code.

Thanks,
Srikanth.P

In reply to srikanth.srivishnav:

property axi_wstrb_default;
            @(posedge clk) disable iff (!rst_n)
           (($rose(rst_n))|-> always (axi_acp_wstrb == 16'hffff);
endproperty

Hi Dave,

Iam facing below error for the standalone code in SV. like always cannot be used.

Error-[SE] Syntax error
Following verilog source has syntax error :
“assertion_trial.sv”, 34: token is ‘always’
(($rose(rstn))|-> always(data == 4’h8));

Thanks,
Srikanth.P

In reply to srikanth.srivishnav:

I want to code an assertion for default value after reset and it should be stable till end of simulation.
like ex:

property axi_wstrb_default;
@(posedge clk) disable iff (!rst_n)
(($rose(rst_n))|-> ((axi_acp_wstrb == 16'hffff) ##[1:$]($stable(axi_acp_wstrb))));
endproperty

Srikanth.P

Could you please show which problem you are facing? Your syntax is correct.

In reply to chr_sue:

I could not able to see the assertion error in my standalone code with my code.

My code:
logic [3:0] data;

initial begin
rst = 1’b0;
#10 rst = 1’b1;
end

initial begin
#10 data = 4’h8;
#500
data = 4’h9;
#100
data = 4’ha;
#1000 $finish;
end

property check_stable_after_rst;
@(posedge clk) disable iff (~rst)

((rose(rst))|-> (data == 4'h8) ##[1:] $stable(data)); ---- this code is not giving the offending error when data =9,
//(($rose(rstn))|-> always(data == 4’h8)); – This code is giving me syntax error for always keyword used.

endproperty

assert property (check_stable_after_rst);

In reply to srikanth.srivishnav:

Could you try this one:

property axi_wstrb_default;
            @(posedge clk) disable iff (!rst_n)
	    (rst_n && (axi_acp_wstrb == 16'hffff)) |-> ##1 (axi_acp_wstrb == 16'hffff)  ##1000 ($stable(axi_acp_wstrb));
endproperty

Dealing with $ in an assertion is not a good coding style. Choose always a reasonable big number as I did (1000).
And you should think about if you can check this behavior together with other signals.
For the property above the simulator has to sample and to store a hugh amount of data which might slow down your simulation.

In reply to chr_sue:

There is a more easy solution:

property axi_wstrb_default;
            @(posedge clk) disable iff (!rst_n)
	    (rst_n && (axi_acp_wstrb == 16'hffff)) |-> ##1 (axi_acp_wstrb == 16'hffff) ;
endproperty

In reply to chr_sue:

But this does not check the default value after the rst toggle, if default value is other than 16’hffff after the rst, then this won’t check that condition or give the error.

In reply to srikanth.srivishnav:

actually i need to check the default value after the rst, and also stability of data till end of simulation.

i can try 2 properties, 1 for checking the default value, and other for stability of the value.

property check_stable_after_rst;
@(posedge clk) disable iff (~rst)
rst |-> stable(data)[*1:];
endproperty

property check_dafault_after_rst;
@(posedge clk) disable iff (~rst)
(($rose(rst)) |-> (data == 4’h8));
endproperty

but is there any way to get properties in single property ?

  1. as per Dave code as below, always is compiling in uvm, but not in normal SV simulation. is there any special packages in uvm to support always property in uvm ?

(($rose(rst_n))|-> always (axi_acp_wstrb == 16’hffff);

In reply to srikanth.srivishnav:

In reply to chr_sue:
But this does not check the default value after the rst toggle, if default value is other than 16’hffff after the rst, then this won’t check that condition or give the error.

That’s right.
It is not a bad coding style to split checking of a certain behavior into more than 1 property.
In contrast, you might get a better simulation behavior.

BTW the always solution is not compiling in my environment, using UVM 1.1d.

In reply to chr_sue:

You are probably using an older version of a tool that does not support the always syntax. This has nothing to do with UVM if you are trying to write this inside an interface or module, not a class.

How about this ?

property axi_wstrb_default;
            @(posedge clk) disable iff (!rst_n)
           (($rose(rst_n))|-> ((axi_acp_wstrb == 16'hffff) ##1 ($stable(axi_acp_wstrb)*[$])));
        endproperty