Array of interface instance

ace_master_interface mst_if[`no_of_masters](aclk,resetn);

for(int i=0;i<`no_of_masters;i++)begin
    	  uvm_config_db #(virtual ace_master_interface)::set(null,"*",$sformatf("mst_if[%0d]",i),mst_if[i]); 
end
Error-[IIXMR] Invalid index in cross-module reference
../hdl/ace_top.sv, 141
  Invalid index in cross-module reference due to index is not constant.
  Argument: mst_if
  Source info: : uvm_config_db::set(null, "*", $sformatf("mst_if[%0d]", i),
  mst_if[i]);
  Instance stack trace:

I’m gettin this error. Please help.
Thanks

In reply to Raja VA:

You have to use a generate like this:

ace_master_interface mst_if[`no_of_masters](aclk,resetn);
 
for(genvar i=0;i<`no_of_masters;i++)begin
   initial 
    	  uvm_config_db #(virtual ace_master_interface)::set(null,"*",$sformatf("mst_if[%0d]",i),mst_if[i]); 
   end

In reply to Raja VA:

Arrays of instances are not true arrays of identically typed data elements and have to be handled specially at elaboration, not dynamically during simulation. Features like parameter overrides and port coercion can potentially make each instance element have different types and structures. The index into a true array is simply a computed offset into memory selecting a uniformly shaped element.

SystemVerilog treats the index of an array of instances (or generate for-loop of instances as part of the scope name. So mst_if[0], mst_if[i], … might as well be mst_if_zero, mst_if_one,…

In reply to Raja VA:


genvar idx;
for(idx = 0; idx < num_inst; idx++) begin
  initial begin : vif_inst
    vif m_vif;
    uvm_config_db #(vif)::set(null,"*",{PRE_FIX,$sformatf("vif[%0d]",idx)},m_vif);
  end
end

//some code...
//use vif 0
vif_inst[0].m_vif.xyz = 0;
//use fix value or <font size=20>genvar</font> if set for all