Approach to disconnect RTL driver and bind AHB interface instead

Question

Hi,

I am having a VHDL DUT where I want to disconnect CPU RTL and bind AHB interface to the interconnect to mimic CPU transactions.

Approach I am using is , connect high 'Z' to CPU related inputs of interconnect and using SV bind statement connect AHB interface to CPU interconnect inputs.

Currently I am getting error related to direction of ports.

But I would like to know whether this approach is better or are there better approaches wherein I must to use bind construct

Answer 1

Srini @ CVCblr.com

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249 posts

November 18, 2015 at 10:39 am

In reply to Chandrashekhar Goudar:

You are dealing with Mixed-language designs/sims - an area that's ill-defined in "standards" and sometimes tool dependent. Having said that - what you are looking for sounds reasonable. I believe tools have ways to do "black-boxing" like what you are looking for. Talk to your vendor (I guess SNPS?).

On the "bind" front - you should be binding to the RTL outputs and not the interconnect inputs (I am assuming CPU-RTL-output --> interconnect-input connection). That way you should be able to attach an external driver via bind.

HTH
Srini
www.verifnews.org

Answer 2

Chandrashekhar Goudar

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22 posts

November 18, 2015 at 10:00 pm

In reply to Srini @ CVCblr.com:

My exact requirement is to bind AHB I/F where I get haddr,hwrite etc stimulus from UVC to interconnect input(vhdl RTL where CPU RTL ports will be connected earlier).

I figured out, AHB I/F logic signals can not be binded to DUT and I created wrapper module around AHB I/F with ports ,and I am connecting that wrapper output to interconnect i/p. VCS elab is not allowing this due to some reason

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