APB write bin not getting hit

UVM
1

I am sampling a coverpoint based on Psel, but it looks like the Read bin and Read after Read gets hit. But for some reason i dont see the write bin getting hit. Here is the sample code. I see in the waves write access are going through.



 covergroup APB_accesses_cg();

//option.per_instance = 1;

RW: coverpoint pwrite {
 // bins read = {0};
  bins write = {1};
 // bins read_after_read = (0[*2]);
  bins write_after_write = (1[*2]);
}
   
endgroup: APB_accesses_cg
   


APB_accesses_cg APB_protocol_cg;
   
   initial begin
     APB_protocol_cg = new();
   end
     
    
    sequence END_OF_APB_TRANSFER;
    @(posedge pclk)
      ($rose(penable & pready),$display("coming here"));
endsequence: END_OF_APB_TRANSFER
    
    
  
 
cover property(END_OF_APB_TRANSFER) begin
  if(psel == 1) begin
      APB_protocol_cg.sample();
    $display ("Entering here in covergroup");
    end
  end

Code

2

In reply to rag123:

Could you please make the EDAPlayground link public?
In your example the cocergroup is not connected to any signal/variable.

3

In reply to chr_sue:

I just changed it. It is inside the interface.

4

In reply to rag123:

Thanks.
Your sampling mechanism does not work. The cover property is never active.
See here

5

In reply to chr_sue:

UVM_INFO testbench.sv(829) @ 1990: uvm_test_top [Coverage_info] Coverage = 0.00 %

6

In reply to rag123:

This is the output of the report_phase and it indicates the covergroup were never sampled.
The sample function is callad in a cover_property like this

cover property(END_OF_APB_TRANSFER) begin
  if(psel == 1) begin
      APB_protocol_cg.sample();
    `uvm_info("prop", "sampled covergroup", UVM_MEDIUM)
  end
end

In the simulation log you do not see this uvm_info, i.e. it is never called and the coverage has to be 0.
Please see here