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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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    • Additional Forums

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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • U2U MARLUG - January 26th
      • Creating an Optimal Safety Architecture  - February 9th
      • The ABC of Formal Verification - February 11th
      • Events Calendar
    • On Demand Seminars

      • I'm Excited About Formal...
      • Visualizer Coverage
      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
      • All On-Demand Seminars
    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings
    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training
    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us
    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
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UVM uvm_reg
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26 questions in UVM

  • TITLE
    SOLVED
    REPLIES
    VIEWS
    POSTED
    UPDATED
  • Uvm_reg_field Individual Byte Access Works in UVM 1.2 but not in UVM IEEE 1800.2-2017
    2  
    88  
    1 week 1 day ago
    by William Moore  
    1 week 23 hours ago
    by William Moore  
  • uvm_reg protocol level error/pio hole err injection
     
    231  
    9 months 2 weeks ago
    by waver123  
    9 months 2 weeks ago
    No activity yet  
  • uvm_reg_file
    1  
    357  
    11 months 1 week ago
    by Eranr  
    11 months 1 week ago
    by chr_sue  
  • get_mirrored_value() mismatch
    4  
    792  
    1 year 1 week ago
    by Bahaa Osman  
    1 year 1 week ago
    by Bahaa Osman  
  • UVM RAL implementation methodology for large designs
     
    405  
    1 year 4 months ago
    by rgarcia07  
    1 year 4 months ago
    No activity yet  
  • X in uvm_reg transactions
    7  
    681  
    1 year 7 months ago
    by vigneshr  
    1 year 6 months ago
    by gariks  
  • Multiple agents accessing a single uvm_reg_block
    2  
    585  
    2 years 2 months ago
    by mpattaje  
    2 years 2 months ago
    by mpattaje  
  • UVM Reg with indirect address map?
    1  
    806  
    2 years 6 months ago
    by davidrogoff  
    2 years 6 months ago
    by manjubshetty  
  • UVM_REG_BLOCK from UVM_REG
    1  
    1,403  
    2 years 8 months ago
    by nikhilverif  
    2 years 8 months ago
    by warnerrs  
  • UVM reg field access via name
    5  
    3,114  
    3 years 6 months ago
    by mayurverf  
    1 year 7 months ago
    by Tudor Timi  
  • How to do uvm built in bit-bash sequence /read-write on Indirect addressed registers?
     
    1,101  
    3 years 8 months ago
    by aditgupta100  
    3 years 8 months ago
    No activity yet  
  • How to print variable of type uvm_reg?
    2  
    2,689  
    4 years 1 month ago
    by sudhirss77  
    4 years 1 month ago
    by sudhirss77  
  • UVM RAL Related
    1  
    993  
    4 years 2 months ago
    by anirban_pande  
    4 years 2 months ago
    by rohitk  
  • uvm_reg::read mirrored value immediately overwritten by subseqent uvm_reg::write
     
    852  
    4 years 5 months ago
    by jhardy  
    4 years 5 months ago
    No activity yet  
  • how to map same register block to multiple interfaces
     
    928  
    4 years 9 months ago
    by sudheer.vemula  
    4 years 9 months ago
    No activity yet  
  • uvm_reg_field::get() usage
     
    1,018  
    4 years 11 months ago
    by anacharya  
    4 years 11 months ago
    No activity yet  
  • OVM to UVM migration of ovm_register_agent layering agent code and ovm_register_sequence_base code
    2  
    1,047  
    5 years 1 month ago
    by akinane  
    5 years 4 weeks ago
    by akinane  
  • Global define UVM_REG_DATA_WIDTH
    3  
    2,843  
    5 years 2 months ago
    by sanjeevs  
    5 years 2 months ago
    by sanjeevs  
  • RAL Concept , Benefits ?
    2  
    9,320  
    5 years 5 months ago
    by withankitgarg  
    5 years 4 months ago
    by An Pham  
  • uvm reg mirror check always passes
    1  
    1,947  
    5 years 5 months ago
    by junettetan  
    5 years 5 months ago
    by junettetan  

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13,421 Questions

40,223 Replies

69,245 Users

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